| /src/sys/external/bsd/drm2/dist/drm/i915/display/ |
| intel_dp_mst.c | 66 crtc_state->pipe_bpp = bpp;
69 crtc_state->pipe_bpp,
85 intel_link_compute_m_n(crtc_state->pipe_bpp,
185 * their current pipe_bpp we should reduce pipe_bpp across
191 limits.max_bpp = min(pipe_config->pipe_bpp, 24);
|
| intel_lvds.c | 296 if (pipe_config->dither && pipe_config->pipe_bpp == 18)
415 if (lvds_bpp != pipe_config->pipe_bpp && !pipe_config->bw_constrained) {
417 pipe_config->pipe_bpp, lvds_bpp);
418 pipe_config->pipe_bpp = lvds_bpp;
|
| intel_ddi.c | 1536 else if (pipe_config->has_hdmi_sink && pipe_config->pipe_bpp > 24)
1537 dotclock = pipe_config->port_clock * 24 / pipe_config->pipe_bpp;
1776 switch (crtc_state->pipe_bpp) {
1790 MISSING_CASE(crtc_state->pipe_bpp);
1845 switch (crtc_state->pipe_bpp) {
4295 pipe_config->pipe_bpp = 18;
4298 pipe_config->pipe_bpp = 24;
4301 pipe_config->pipe_bpp = 30;
4304 pipe_config->pipe_bpp = 36;
4380 pipe_config->pipe_bpp > dev_priv->vbt.edp.bpp)
[all...] |
| intel_hdmi.c | 936 static bool gcp_default_phase_possible(int pipe_bpp,
941 switch (pipe_bpp) {
1031 if (crtc_state->pipe_bpp > 24)
1035 if (gcp_default_phase_possible(crtc_state->pipe_bpp,
1760 if (crtc_state->pipe_bpp > 24)
1930 if (pipe_config->pipe_bpp > 24 &&
1976 if (pipe_config->pipe_bpp > 24) {
1988 if (pipe_config->pipe_bpp > 24) {
2233 if (crtc_state->pipe_bpp < bpc * 3)
2361 * pipe_bpp could already be below 8bpc due t
[all...] |
| intel_dp.c | 1938 bpp = pipe_config->pipe_bpp;
1970 DRM_DEBUG_KMS("Setting pipe_bpp to %d\n", bpp);
2032 pipe_config->pipe_bpp = bpp;
2125 int pipe_bpp; local in function:intel_dp_dsc_compute_config
2141 pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp, dsc_max_bpc);
2144 if (pipe_bpp < 8 * 3) {
2154 pipe_config->pipe_bpp = pipe_bpp;
2161 pipe_config->pipe_bpp);
2185 pipe_config->pipe_bpp);
[all...] |
| icl_dsi.c | 1335 pipe_config->pipe_bpp = bdw_get_pipemisc_bpp(crtc);
1351 if (crtc_state->pipe_bpp < 8 * 3)
1406 pipe_config->pipe_bpp = 24;
1408 pipe_config->pipe_bpp = 18;
|
| intel_audio.c | 269 if (crtc_state->pipe_bpp == 36) {
272 } else if (crtc_state->pipe_bpp == 30) {
|
| intel_crt.c | 421 if (pipe_config->bw_constrained && pipe_config->pipe_bpp < 24) {
426 pipe_config->pipe_bpp = 24;
|
| intel_display.c | 7732 pipe_config->pipe_bpp);
7736 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
7743 if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) {
7744 pipe_config->pipe_bpp -= 2*3;
7746 pipe_config->pipe_bpp);
7771 if (crtc_state->pipe_bpp > 24)
8791 if (crtc_state->dither && crtc_state->pipe_bpp != 30)
8795 switch (crtc_state->pipe_bpp) {
9267 pipe_config->pipe_bpp = 18;
9270 pipe_config->pipe_bpp = 24
[all...] |
| vlv_dsi.c | 294 pipe_config->pipe_bpp = 24;
296 pipe_config->pipe_bpp = 18;
1067 pipe_config->pipe_bpp = bdw_get_pipemisc_bpp(crtc);
|
| intel_psr.c | 662 if (crtc_state->pipe_bpp > max_bpp) {
664 crtc_state->pipe_bpp, max_bpp);
|
| intel_bios.c | 2441 crtc_state->pipe_bpp = bpc * 3;
2443 crtc_state->dsc.compressed_bpp = min(crtc_state->pipe_bpp,
|
| intel_display_types.h | 922 int pipe_bpp; member in struct:intel_crtc_state
|
| intel_vdsc.c | 407 vdsc_cfg->bits_per_component = pipe_config->pipe_bpp / 3;
|
| intel_tv.c | 1209 pipe_config->pipe_bpp = 8*3;
|
| intel_panel.c | 448 if (INTEL_GEN(dev_priv) < 4 && pipe_config->pipe_bpp == 18)
|
| intel_sdvo.c | 1288 pipe_config->pipe_bpp = 8*3;
|
| /src/sys/external/bsd/drm2/dist/drm/i915/ |
| i915_debugfs.c | 2648 yesno(crtc_state->dither), crtc_state->pipe_bpp);
|
