| /src/sys/arch/arm/nxp/ |
| imx_ccm_pll.c | 48 struct imx_ccm_pll *pll = &clk->u.pll; local in function:imx_ccm_pll_enable
53 if ((pll->flags & IMX_PLL_ENET) != 0)
58 val = CCM_READ(sc, clk->regidx, pll->reg);
63 CCM_WRITE(sc, clk->regidx, pll->reg, val);
72 struct imx_ccm_pll *pll= &clk->u.pll; local in function:imx_ccm_pll_get_rate
86 if ((pll->flags & IMX_PLL_ENET) != 0) {
87 /* For ENET PLL, div_mask contains the fixed output rate */
88 return pll->div_mask
109 struct imx_ccm_pll *pll = &clk->u.pll; local in function:imx_ccm_pll_get_parent
[all...] |
| imx6_ccm.c | 161 struct imx6_clk_pll *pll = &iclk->clk.pll; local in function:imxccm_clk_get_rate_pll_generic
164 KASSERT((pll->type == IMX6_CLK_PLL_GENERIC) ||
165 (pll->type == IMX6_CLK_PLL_USB));
167 uint32_t v = bus_space_read_4(sc->sc_iot, sc->sc_ioh_analog, pll->reg);
168 uint32_t div = __SHIFTOUT(v, pll->mask);
177 struct imx6_clk_pll *pll = &iclk->clk.pll; local in function:imxccm_clk_get_rate_pll_sys
180 KASSERT(pll->type == IMX6_CLK_PLL_SYS);
182 uint32_t v = bus_space_read_4(sc->sc_iot, sc->sc_ioh_analog, pll->reg)
195 struct imx6_clk_pll *pll = &iclk->clk.pll; local in function:imxccm_clk_get_rate_pll_audio_video
216 struct imx6_clk_pll *pll = &iclk->clk.pll; local in function:imxccm_clk_get_rate_pll_enet
242 struct imx6_clk_pll *pll = &iclk->clk.pll; local in function:imxccm_clk_get_rate_pll
538 struct imx6_clk_pll *pll = &iclk->clk.pll; local in function:imxccm_clk_enable_pll
[all...] |
| /src/sys/arch/arm/amlogic/ |
| meson_clk_pll.c | 43 struct meson_clk_pll *pll = &clk->u.pll; local in function:meson_clk_pll_get_rate
62 val = CLK_READ(sc, pll->n.reg);
63 n = __SHIFTOUT(val, pll->n.mask);
65 val = CLK_READ(sc, pll->m.reg);
66 m = __SHIFTOUT(val, pll->m.mask);
68 if (pll->frac.mask) {
69 val = CLK_READ(sc, pll->frac.reg);
70 frac = __SHIFTOUT(val, pll->frac.mask);
80 rate += howmany(frac_rate, __SHIFTOUT_MASK(pll->frac.mask) + 1)
102 struct meson_clk_pll *pll = &clk->u.pll; local in function:meson_clk_pll_set_rate
177 struct meson_clk_pll *pll = &clk->u.pll; local in function:meson_clk_pll_get_parent
[all...] |
| meson_clk.h | 229 * PLL clocks
259 struct meson_clk_pll *pll);
267 .u.pll.parent = (_parent), \
268 .u.pll.enable = _enable, \
269 .u.pll.m = _m, \
270 .u.pll.n = _n, \
271 .u.pll.frac = _frac, \
272 .u.pll.l = _l, \
273 .u.pll.reset = _reset, \
274 .u.pll.flags = (_flags),
341 struct meson_clk_pll pll; member in union:meson_clk_clk::__anon83605c73010a
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/ |
| amdgpu_pll.c | 109 * amdgpu_pll_compute - compute PLL paramaters
111 * @pll: information about the PLL
118 * Try to calculate the PLL parameters to generate the given frequency:
121 void amdgpu_pll_compute(struct amdgpu_pll *pll,
129 unsigned target_clock = pll->flags & AMDGPU_PLL_USE_FRAC_FB_DIV ?
139 fb_div_min = pll->min_feedback_div;
140 fb_div_max = pll->max_feedback_div;
142 if (pll->flags & AMDGPU_PLL_USE_FRAC_FB_DIV) {
148 if (pll->flags & AMDGPU_PLL_USE_REF_DIV
[all...] |
| amdgpu_pll.h | 29 void amdgpu_pll_compute(struct amdgpu_pll *pll,
|
| /src/sys/dev/i2c/ |
| tvpll.c | 47 const struct tvpll_data * pll; member in struct:tvpll
63 tvpll->pll = p;
65 if (tvpll->pll->initdata) {
68 &tvpll->pll->initdata[1], tvpll->pll->initdata[0],
73 device_printf(parent, "tvpll: %s\n", tvpll->pll->name);
88 const struct tvpll_data *pll; local in function:tvpll_algo
92 pll = tvpll->pll;
95 (p->frequency < pll->min || p->frequency > pll->max)
[all...] |
| /src/sys/arch/arm/rockchip/ |
| rk_cru_pll.c | 90 struct rk_cru_pll *pll = &clk->u.pll; local in function:rk_cru_pll_get_rate
105 const uint32_t con0 = CRU_READ(sc, pll->con_base + PLL_CON0);
106 const uint32_t con1 = CRU_READ(sc, pll->con_base + PLL_CON1);
107 const uint32_t con2 = CRU_READ(sc, pll->con_base + PLL_CON2);
108 const uint32_t con3 = CRU_READ(sc, pll->con_base + PLL_CON3);
110 if ((pll->flags & RK_PLL_RK3288) != 0) {
122 } else if ((pll->flags & RK_PLL_RK3588) != 0) {
160 struct rk_cru_pll *pll = &clk->u.pll; local in function:rk_cru_pll_set_rate
277 struct rk_cru_pll *pll = &clk->u.pll; local in function:rk_cru_pll_get_parent
[all...] |
| rk3399_pmucru.c | 164 struct rk_cru_pll *pll = &clk->u.pll; local in function:rk3399_pmucru_pll_get_rate
179 const uint32_t con0 = CRU_READ(sc, pll->con_base + PLL_CON0);
180 const uint32_t con1 = CRU_READ(sc, pll->con_base + PLL_CON1);
181 const uint32_t con2 = CRU_READ(sc, pll->con_base + PLL_CON2);
182 const uint32_t con3 = CRU_READ(sc, pll->con_base + PLL_CON3);
207 struct rk_cru_pll *pll = &clk->u.pll; local in function:rk3399_pmucru_pll_set_rate
214 if (pll->rates == NULL || rate == 0)
217 for (int i = 0; i < pll->nrates; i++
[all...] |
| rk3399_cru.c | 236 struct rk_cru_pll *pll = &clk->u.pll; local in function:rk3399_cru_pll_get_rate
251 const uint32_t con0 = CRU_READ(sc, pll->con_base + PLL_CON0);
252 const uint32_t con1 = CRU_READ(sc, pll->con_base + PLL_CON1);
253 const uint32_t con2 = CRU_READ(sc, pll->con_base + PLL_CON2);
254 const uint32_t con3 = CRU_READ(sc, pll->con_base + PLL_CON3);
279 struct rk_cru_pll *pll = &clk->u.pll; local in function:rk3399_cru_pll_set_rate
286 if (pll->rates == NULL || rate == 0)
290 for (int i = 0; i < pll->nrates; i++)
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/nouveau/nvkm/subdev/clk/ |
| nouveau_nvkm_subdev_clk_gk20a.c | 70 gk20a_pllg_read_mnp(struct gk20a_clk *clk, struct gk20a_pll *pll)
76 pll->m = (val >> GPCPLL_COEFF_M_SHIFT) & MASK(GPCPLL_COEFF_M_WIDTH);
77 pll->n = (val >> GPCPLL_COEFF_N_SHIFT) & MASK(GPCPLL_COEFF_N_WIDTH);
78 pll->pl = (val >> GPCPLL_COEFF_P_SHIFT) & MASK(GPCPLL_COEFF_P_WIDTH);
82 gk20a_pllg_write_mnp(struct gk20a_clk *clk, const struct gk20a_pll *pll)
87 val = (pll->m & MASK(GPCPLL_COEFF_M_WIDTH)) << GPCPLL_COEFF_M_SHIFT;
88 val |= (pll->n & MASK(GPCPLL_COEFF_N_WIDTH)) << GPCPLL_COEFF_N_SHIFT;
89 val |= (pll->pl & MASK(GPCPLL_COEFF_P_WIDTH)) << GPCPLL_COEFF_P_SHIFT;
94 gk20a_pllg_calc_rate(struct gk20a_clk *clk, struct gk20a_pll *pll)
99 rate = clk->parent_rate * pll->n
220 struct gk20a_pll pll; local in function:gk20a_pllg_slide
470 struct gk20a_pll pll; local in function:gk20a_clk_read
555 struct gk20a_pll pll; local in function:gk20a_clk_fini
[all...] |
| gt215.h | 10 u32 pll; member in struct:gt215_clk_info
|
| nouveau_nvkm_subdev_clk_gm20b.c | 165 gm20b_pllg_read_mnp(struct gm20b_clk *clk, struct gm20b_pll *pll)
171 gk20a_pllg_read_mnp(&clk->base, &pll->base);
173 pll->sdm_din = (val >> GPCPLL_CFG2_SDM_DIN_SHIFT) &
178 gm20b_pllg_write_mnp(struct gm20b_clk *clk, const struct gm20b_pll *pll)
183 pll->sdm_din << GPCPLL_CFG2_SDM_DIN_SHIFT);
184 gk20a_pllg_write_mnp(&clk->base, &pll->base);
190 * limit "0" (to make sure that PLL output remains under F/V curve when
275 struct gm20b_pll pll; local in function:gm20b_pllg_slide
283 gm20b_pllg_read_mnp(clk, &pll);
285 if (n_int == pll.base.n && sdm_din == pll.sdm_din
732 struct gk20a_pll pll; local in function:gm20b_clk_fini
[all...] |
| nouveau_nvkm_subdev_clk_gt215.c | 32 #include "pll.h"
36 #include <subdev/bios/pll.h>
113 read_pll(struct gt215_clk *clk, int idx, u32 pll)
116 u32 ctrl = nvkm_rd32(device, pll + 0);
122 u32 coef = nvkm_rd32(device, pll + 4);
130 if ((pll & 0x00ff00) == 0x00e800)
225 * and the VBIOS on my NVA8 seem to prefer using the PLL
240 gt215_pll_info(struct nvkm_clk *base, int idx, u32 pll, u32 khz,
249 info->pll = 0;
252 * PLL and use the divider instead. *
[all...] |
| gk20a.h | 121 struct gk20a_pll pll; member in struct:gk20a_clk
145 gk20a_pllg_n_lo(struct gk20a_clk *clk, struct gk20a_pll *pll)
147 return DIV_ROUND_UP(pll->m * clk->params->min_vco,
|
| /src/sys/external/bsd/drm2/dist/drm/i915/display/ |
| intel_dpll_mgr.c | 39 * per-pipe or per-encoder dedicated PLLs, others allow the use of any PLL
41 * share a PLL if their configurations match.
45 * users of a PLL are tracked and that tracking is integrated with the atomic
63 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; local in function:intel_atomic_duplicate_dpll_state
65 shared_dpll[i] = pll->state;
89 * @id: pll id
104 * @pll: the DPLL
107 * The id of @pll
111 struct intel_shared_dpll *pll)
113 if (WARN_ON(pll < dev_priv->shared_dplls|
148 struct intel_shared_dpll *pll = crtc_state->shared_dpll; local in function:intel_prepare_shared_dpll
175 struct intel_shared_dpll *pll = crtc_state->shared_dpll; local in function:intel_enable_shared_dpll
220 struct intel_shared_dpll *pll = crtc_state->shared_dpll; local in function:intel_disable_shared_dpll
260 struct intel_shared_dpll *pll, *unused_pll = NULL; local in function:intel_find_shared_dpll
368 struct intel_shared_dpll *pll = local in function:intel_shared_dpll_swap_state
461 struct intel_shared_dpll *pll; local in function:ibx_get_dpll
826 struct intel_shared_dpll *pll; local in function:hsw_ddi_hdmi_get_dpll
853 struct intel_shared_dpll *pll; local in function:hsw_ddi_dp_get_dpll
886 struct intel_shared_dpll *pll; local in function:hsw_get_dpll
1452 struct intel_shared_dpll *pll; local in function:skl_get_dpll
1902 struct intel_shared_dpll *pll; local in function:bxt_get_dpll
2405 struct intel_shared_dpll *pll; local in function:cnl_get_dpll
[all...] |
| intel_dpll_mgr.h | 128 * @DPLL_ID_ICL_TBTPLL: ICL/TGL TBT PLL
132 * @DPLL_ID_ICL_MGPLL1: ICL MG PLL 1 port 1 (C),
133 * TGL TC PLL 1 port 1 (TC1)
137 * @DPLL_ID_ICL_MGPLL2: ICL MG PLL 1 port 2 (D)
138 * TGL TC PLL 1 port 2 (TC2)
142 * @DPLL_ID_ICL_MGPLL3: ICL MG PLL 1 port 3 (E)
143 * TGL TC PLL 1 port 3 (TC3)
147 * @DPLL_ID_ICL_MGPLL4: ICL MG PLL 1 port 4 (F)
148 * TGL TC PLL 1 port 4 (TC4)
152 * @DPLL_ID_TGL_MGPLL5: TGL TC PLL port 5 (TC5
[all...] |
| /src/sys/external/gpl2/dts/dist/arch/mips/boot/dts/qca/ |
| ar9132.dtsi | 17 clocks = <&pll ATH79_CLK_CPU>;
64 clocks = <&pll ATH79_CLK_AHB>;
89 pll: pll-controller@18050000 { label
90 compatible = "qca,ar9132-pll",
91 "qca,ar9130-pll";
107 clocks = <&pll ATH79_CLK_AHB>;
151 clocks = <&pll ATH79_CLK_AHB>;
|
| ar9331.dtsi | 17 clocks = <&pll ATH79_CLK_CPU>;
90 pll: pll-controller@18050000 { label
91 compatible = "qca,ar9330-pll";
126 clocks = <&pll ATH79_CLK_AHB>, <&pll ATH79_CLK_AHB>;
141 clocks = <&pll ATH79_CLK_AHB>, <&pll ATH79_CLK_AHB>;
281 clocks = <&pll ATH79_CLK_AHB>;
|
| /src/sys/external/bsd/drm2/dist/drm/radeon/ |
| radeon_display.c | 941 * radeon_compute_pll_avivo - compute PLL paramaters
943 * @pll: information about the PLL
950 * Try to calculate the PLL parameters to generate the given frequency:
953 void radeon_compute_pll_avivo(struct radeon_pll *pll,
961 unsigned target_clock = pll->flags & RADEON_PLL_USE_FRAC_FB_DIV ?
971 fb_div_min = pll->min_feedback_div;
972 fb_div_max = pll->max_feedback_div;
974 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) {
980 if (pll->flags & RADEON_PLL_USE_REF_DIV
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/nouveau/nvkm/subdev/devinit/ |
| nouveau_nvkm_subdev_devinit_gv100.c | 30 #include <subdev/bios/pll.h>
31 #include <subdev/clk/pll.h>
|
| /src/sys/external/gpl2/dts/dist/arch/arm/boot/dts/ |
| keystone-k2e-clocks.dtsi | 11 compatible = "ti,keystone,main-pll-clock";
19 compatible = "ti,keystone,pll-clock";
28 compatible = "ti,keystone,pll-clock";
30 clock-output-names = "ddr-3a-pll-clk";
|
| /src/sys/external/bsd/drm2/dist/drm/nouveau/nvkm/subdev/fb/ |
| nouveau_nvkm_subdev_fb_ramnv40.c | 34 #include <subdev/bios/pll.h>
35 #include <subdev/clk/pll.h>
44 struct nvbios_pll pll; local in function:nv40_ram_calc
48 ret = nvbios_pll_parse(bios, 0x04, &pll);
50 nvkm_error(subdev, "mclk pll data not found\n");
54 ret = nv04_pll_calc(subdev, &pll, freq, &N1, &M1, &N2, &M2, &log2P);
59 ram->ctrl |= min(pll.bias_p + log2P, (int)pll.max_p) << 20;
127 /* change the PLL of each memory partition */
|
| /src/sys/arch/mips/atheros/ |
| ar9344.c | 124 uint32_t pll; local in function:ar9344_get_freqs
137 * Let's figure out the CPU PLL frequency.
139 pll = GETPLLREG(ARCHIP_PLL_CPU_PLL_CONFIG);
140 out_div = __SHIFTOUT(pll, AR9344_CPU_PLL_CONFIG_OUTDIV);
141 ref_div = __SHIFTOUT(pll, AR9344_CPU_PLL_CONFIG_REFDIV);
142 nint = __SHIFTOUT(pll, AR9344_CPU_PLL_CONFIG_NINT);
143 //nfrac = __SHIFTOUT(pll, AR9344_CPU_PLL_CONFIG_NFRAC);
148 * Now figure out the DDR PLL frequency.
150 pll = GETPLLREG(ARCHIP_PLL_DDR_PLL_CONFIG);
151 out_div = __SHIFTOUT(pll, AR9344_DDR_PLL_CONFIG_OUTDIV)
[all...] |
| /src/sys/arch/arm/nvidia/ |
| tegra_clock.h | 82 struct tegra_pll_clk pll; member in union:tegra_clk::__anon56bd0515010a
|
