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    Searched refs:reference_divider (Results 1 - 13 of 13) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/display/include/
bios_parser_types.h 202 uint32_t reference_divider; member in struct:bp_adjust_pixel_clock_parameters
219 uint32_t reference_divider; member in struct:bp_pixel_clock_parameters
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/inc/
clock_source.h 114 uint32_t reference_divider; member in struct:pll_settings
  /src/sys/external/bsd/drm2/dist/drm/radeon/
radeon_rv730_dpm.c 57 u32 reference_divider, post_divider; local in function:rv730_populate_sclk_value
66 reference_divider = 1 + dividers.ref_div;
74 tmp = (u64) engine_clock * reference_divider * post_divider * 16384;
101 u32 clk_s = reference_clock * 5 / (reference_divider * ss.rate);
136 u32 post_divider, reference_divider; local in function:rv730_populate_mclk_value
144 reference_divider = dividers.ref_div + 1;
177 u32 clk_s = reference_clock * 5 / (reference_divider * ss.rate);
radeon_rv740_dpm.c 137 u32 reference_divider; local in function:rv740_populate_sclk_value
146 reference_divider = 1 + dividers.ref_div;
148 tmp = (u64) engine_clock * reference_divider * dividers.post_div * 16384;
169 u32 clk_s = reference_clock * 5 / (reference_divider * ss.rate);
radeon_rv770_dpm.c 329 u32 post_divider, reference_divider, feedback_divider8; local in function:rv770_calculate_fractional_mpll_feedback_divider
338 reference_divider = dividers->ref_div;
341 (8 * fyclk * reference_divider * post_divider) / reference_clock;
506 u32 reference_divider, post_divider; local in function:rv770_populate_sclk_value
515 reference_divider = 1 + dividers.ref_div;
522 tmp = (u64) engine_clock * reference_divider * post_divider * 16384;
548 u32 clk_s = reference_clock * 5 / (reference_divider * ss.rate);
radeon_ni_dpm.c 2017 u32 reference_divider; local in function:ni_calculate_sclk_params
2026 reference_divider = 1 + dividers.ref_div;
2029 tmp = (u64) engine_clock * reference_divider * dividers.post_div * 16834;
2050 u32 clk_s = reference_clock * 5 / (reference_divider * ss.rate);
radeon_ci_dpm.c 3176 u32 reference_divider; local in function:ci_calculate_sclk_params
3186 reference_divider = 1 + dividers.ref_div;
3199 u32 clk_s = reference_clock * 5 / (reference_divider * ss.rate);
radeon_si_dpm.c 4800 u32 reference_divider; local in function:si_calculate_sclk_params
4809 reference_divider = 1 + dividers.ref_div;
4811 tmp = (u64) engine_clock * reference_divider * dividers.post_div * 16384;
4832 u32 clk_s = reference_clock * 5 / (reference_divider * ss.rate);
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce/
amdgpu_dce_clock_source.c 242 pll_settings->reference_divider = ref_divider;
342 if (pll_settings->reference_divider) {
343 min_ref_divider = pll_settings->reference_divider;
344 max_ref_divider = pll_settings->reference_divider;
457 pll_settings->reference_divider =
458 bp_adjust_pixel_clock_params.reference_divider;
701 pll_settings->reference_divider * ss_data->modulation_freq_hz);
870 bp_pc_params.reference_divider = pll_settings->reference_divider;
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/bios/
amdgpu_command_table.c 962 cpu_to_le16((uint16_t)bp_params->reference_divider);
1033 (uint8_t)(bp_params->reference_divider);
1109 (uint8_t) bp_params->reference_divider;
1525 bp_params->reference_divider = params.sOutput.ucRefDiv;
  /src/sys/external/bsd/drm2/dist/drm/amd/powerplay/smumgr/
amdgpu_iceland_smumgr.c 811 uint32_t reference_divider; local in function:iceland_calculate_sclk_params
824 reference_divider = 1 + dividers.uc_pll_ref_div;
854 uint32_t clkS = reference_clock * 5 / (reference_divider * ss_info.speed_spectrum_rate);
1128 /* tmp = (freq_nom / reference_clock * reference_divider) ^ 2 Note: S.I. reference_divider = 1*/
1135 /* CLKS = reference_clock / (2 * speed_spectrum_rate * reference_divider) * 10 */
amdgpu_tonga_smumgr.c 554 uint32_t reference_divider; local in function:tonga_calculate_sclk_params
567 reference_divider = 1 + dividers.uc_pll_ref_div;
597 uint32_t clkS = reference_clock * 5 / (reference_divider * ss_info.speed_spectrum_rate);
880 /* tmp = (freq_nom / reference_clock * reference_divider) ^ 2 Note: S.I. reference_divider = 1*/
887 /* CLKS = reference_clock / (2 * speed_spectrum_rate * reference_divider) * 10 */
  /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_si_dpm.c 5264 u32 reference_divider; local in function:si_calculate_sclk_params
5273 reference_divider = 1 + dividers.ref_div;
5275 tmp = (u64) engine_clock * reference_divider * dividers.post_div * 16384;
5296 u32 clk_s = reference_clock * 5 / (reference_divider * ss.rate);

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