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    Searched refs:rlc (Results 1 - 20 of 20) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_rlc.c 36 * amdgpu_gfx_rlc_enter_safe_mode - Set RLC into safe mode
40 * Set RLC enter into safe mode if RLC is enabled and haven't in safe mode.
44 if (adev->gfx.rlc.in_safe_mode)
47 /* if RLC is not enabled, do nothing */
48 if (!adev->gfx.rlc.funcs->is_rlc_enabled(adev))
54 adev->gfx.rlc.funcs->set_safe_mode(adev);
55 adev->gfx.rlc.in_safe_mode = true;
60 * amdgpu_gfx_rlc_exit_safe_mode - Set RLC out of safe mode
64 * Set RLC exit safe mode if RLC is enabled and have entered into safe mode
    [all...]
amdgpu_gfx_v10_0.c 577 kfree(adev->gfx.rlc.register_list_format);
612 adev->gfx.rlc.save_restore_list_cntl_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_cntl_size_bytes);
613 adev->gfx.rlc.save_restore_list_cntl = (const u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_cntl_offset_bytes);
616 adev->gfx.rlc.save_restore_list_gpm_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_gpm_size_bytes);
617 adev->gfx.rlc.save_restore_list_gpm = (const u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_gpm_offset_bytes);
620 adev->gfx.rlc.save_restore_list_srm_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_srm_size_bytes);
621 adev->gfx.rlc.save_restore_list_srm = (const u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_srm_offset_bytes);
622 adev->gfx.rlc.reg_list_format_direct_reg_list_length =
733 adev->gfx.rlc.is_rlc_v2_1 = true;
737 adev->gfx.rlc.save_and_restore_offset
    [all...]
amdgpu_gfx_v9_0.c 1087 kfree(adev->gfx.rlc.register_list_format);
1097 adev->gfx.rlc.save_restore_list_cntl_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_cntl_size_bytes);
1098 adev->gfx.rlc.save_restore_list_cntl = (const u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_cntl_offset_bytes);
1101 adev->gfx.rlc.save_restore_list_gpm_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_gpm_size_bytes);
1102 adev->gfx.rlc.save_restore_list_gpm = (const u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_gpm_offset_bytes);
1105 adev->gfx.rlc.save_restore_list_srm_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_srm_size_bytes);
1106 adev->gfx.rlc.save_restore_list_srm = (const u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_srm_offset_bytes);
1107 adev->gfx.rlc.reg_list_format_direct_reg_list_length =
1226 !adev->gfx.rlc.is_rlc_v2_1))
1368 adev->gfx.rlc.is_rlc_v2_1 = true
    [all...]
amdgpu_ucode.c 126 DRM_DEBUG("RLC\n");
212 DRM_ERROR("Unknown RLC ucode version: %u.%u\n", version_major, version_minor);
536 ucode->ucode_size = adev->gfx.rlc.save_restore_list_cntl_size_bytes;
537 memcpy(ucode->kaddr, adev->gfx.rlc.save_restore_list_cntl,
540 ucode->ucode_size = adev->gfx.rlc.save_restore_list_gpm_size_bytes;
541 memcpy(ucode->kaddr, adev->gfx.rlc.save_restore_list_gpm,
544 ucode->ucode_size = adev->gfx.rlc.save_restore_list_srm_size_bytes;
545 memcpy(ucode->kaddr, adev->gfx.rlc.save_restore_list_srm,
amdgpu_gfx_v6_0.c 2066 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) {
2388 adev->gfx.rlc.reg_list = verde_rlc_save_restore_register_list;
2389 adev->gfx.rlc.reg_list_size =
2392 adev->gfx.rlc.cs_data = si_cs_data;
2393 src_ptr = adev->gfx.rlc.reg_list;
2394 dws = adev->gfx.rlc.reg_list_size;
2395 cs_data = adev->gfx.rlc.cs_data;
2406 adev->gfx.rlc.clear_state_size = gfx_v6_0_get_csb_size(adev);
2407 dws = adev->gfx.rlc.clear_state_size + (256 / 4);
2411 &adev->gfx.rlc.clear_state_obj
    [all...]
amdgpu_gfx_v7_0.c 2565 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) {
3304 * RLC
3305 * The RLC is a multi-purpose microengine that handles a
3315 /* allocate rlc buffers */
3318 adev->gfx.rlc.reg_list = spectre_rlc_save_restore_register_list;
3319 adev->gfx.rlc.reg_list_size =
3322 adev->gfx.rlc.reg_list = kalindi_rlc_save_restore_register_list;
3323 adev->gfx.rlc.reg_list_size =
3327 adev->gfx.rlc.cs_data = ci_cs_data;
3328 adev->gfx.rlc.cp_table_size = ALIGN(CP_ME_TABLE_SIZE * 5 * 4, 2048); /* CP JT *
    [all...]
amdgpu_gfx_v8_0.c 99 BPM_REG_CGLS_ON, /* ON/OFF CGLS: shall be controlled by RLC FW */
954 kfree(adev->gfx.rlc.register_list_format);
1083 adev->gfx.rlc.save_and_restore_offset =
1085 adev->gfx.rlc.clear_state_descriptor_offset =
1087 adev->gfx.rlc.avail_scratch_ram_locations =
1089 adev->gfx.rlc.reg_restore_list_size =
1091 adev->gfx.rlc.reg_list_format_start =
1093 adev->gfx.rlc.reg_list_format_separate_start =
1095 adev->gfx.rlc.starting_offsets_start =
1097 adev->gfx.rlc.reg_list_format_size_bytes
    [all...]
amdgpu_ucode.h 273 struct rlc_firmware_header_v1_0 rlc; member in union:amdgpu_firmware_header
amdgpu_gfx.h 244 struct amdgpu_rlc rlc; member in struct:amdgpu_gfx
257 const struct firmware *rlc_fw; /* RLC firmware */
  /src/usr.sbin/altq/libaltq/
qop_jobs.h 100 int64_t rlc; member in struct:jobs_classinfo
111 int64_t adc, int64_t rdc, int64_t alc, int64_t rlc, int64_t arc,
114 int64_t adc, int64_t rdc, int64_t alc, int64_t rlc, int64_t arc);
119 int64_t adc, int64_t rdc, int64_t alc, int64_t rlc, int64_t arc,
122 int64_t adc, int64_t rdc, int64_t alc, int64_t rlc, int64_t arc);
qop_jobs.c 195 int64_t adc, rdc, alc, rlc, arc; local in function:jobs_class_parser
205 rlc = -1;
245 } else if (EQUAL(*argv, "rlc")) {
249 rlc = -1;
251 rlc = strtol(*argv, NULL, 0);
273 adc, rdc, alc, rlc, arc, flags);
300 int64_t adc, int64_t rdc, int64_t alc, int64_t rlc, int64_t arc,
311 pri, adc, rdc, alc, rlc, arc, flags);
330 if (rlc > 0)
331 sprintf(name_rlc,"%d",(int)rlc);
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  /src/sys/external/bsd/drm2/dist/drm/radeon/
radeon_evergreen.c 4032 /* halt the rlc */
4110 * RLC
4120 if (rdev->rlc.save_restore_obj) {
4121 r = radeon_bo_reserve(rdev->rlc.save_restore_obj, false);
4123 dev_warn(rdev->dev, "(%d) reserve RLC sr bo failed\n", r);
4124 radeon_bo_unpin(rdev->rlc.save_restore_obj);
4125 radeon_bo_unreserve(rdev->rlc.save_restore_obj);
4127 radeon_bo_unref(&rdev->rlc.save_restore_obj);
4128 rdev->rlc.save_restore_obj = NULL;
4132 if (rdev->rlc.clear_state_obj)
    [all...]
radeon_ucode.h 47 /* RLC */
217 struct rlc_firmware_header_v1_0 rlc; member in union:radeon_firmware_header
radeon_cik.c 4970 /* stop the rlc */
5193 /* halt the rlc, disable cp internal ints */
5543 /* XXX SDMA RLC - todo */
5780 * RLC
5781 * The RLC is a multi-purpose microengine that handles a
5834 static void cik_update_rlc(struct radeon_device *rdev, u32 rlc)
5839 if (tmp != rlc)
5840 WREG32(RLC_CNTL, rlc);
5897 * cik_rlc_stop - stop the RLC ME
5901 * Halt the RLC ME (MicroEngine) (CIK)
    [all...]
radeon_si.c 3883 /* stop the rlc */
4067 /* halt the rlc, disable cp internal ints */
4941 block = "RLC";
5058 block = "RLC";
5228 static void si_update_rlc(struct radeon_device *rdev, u32 rlc)
5233 if (tmp != rlc)
5234 WREG32(RLC_CNTL, rlc);
5290 WREG32(RLC_SAVE_AND_RESTORE_BASE, rdev->rlc.save_restore_gpu_addr >> 8);
5296 WREG32(RLC_CLEAR_STATE_RESTORE_BASE, rdev->rlc.clear_state_gpu_addr >> 8);
5696 if (rdev->rlc.cs_data == NULL
    [all...]
radeon_ni.c 2195 /* allocate rlc buffers */
2197 rdev->rlc.reg_list = tn_rlc_save_restore_register_list;
2198 rdev->rlc.reg_list_size =
2200 rdev->rlc.cs_data = cayman_cs_data;
2203 DRM_ERROR("Failed to init rlc BOs!\n");
2673 block = "RLC";
radeon.h 1028 * RLC stuff
2460 const struct firmware *rlc_fw; /* r6/700 RLC firmware */
2473 struct radeon_rlc rlc; member in struct:radeon_device
  /src/sys/dev/qbus/
rl.c 77 CFATTACH_DECL_NEW(rlc, sizeof(struct rlc_softc),
  /src/sys/altq/
altq_jobs.c 259 int64_t alc, int64_t rlc, int64_t arc, int flags)
333 if (rlc == -1) {
334 rlc = 0;
359 cl->cl_rlc=rlc;
807 * no ALC, no RLC on this class:
820 * no RLC, but an ALC:
876 * RLC on that class:
1726 * means "ignore RLC" here)
1775 * the RLC will defeat the ALC:
1776 * ignore RLC
    [all...]
  /src/sys/external/bsd/drm2/dist/drm/amd/powerplay/
amdgpu_smu.c 1416 * RLC on those ASICs. RLC reinitialization will be
1498 adev->gfx.rlc.funcs->stop)
1499 adev->gfx.rlc.funcs->stop(adev);

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