| /src/sys/arch/arm/nxp/ |
| imx_ccm.c | 55 clk = &sc->sc_clks[i];
234 if (sc->sc_clks[i].base.name == NULL)
236 if (strcmp(sc->sc_clks[i].base.name, name) == 0)
237 return &sc->sc_clks[i];
263 sc->sc_clks[i].base.domain = &sc->sc_clkdom;
264 clk_attach(&sc->sc_clks[i].base);
282 clk = &sc->sc_clks[i];
|
| imx8mq_ccm.c | 197 sc->sc_clks = imx8mq_ccm_clks;
|
| /src/sys/arch/arm/sunxi/ |
| sun50i_a64_ccu.c | 629 sc->sc_clks = sun50i_a64_ccu_clks;
640 clk_set_parent(&sc->sc_clks[A64_CLK_DE].base, &sc->sc_clks[A64_CLK_PLL_DE].base);
641 clk_set_rate(&sc->sc_clks[A64_CLK_PLL_DE].base, 420000000);
644 clk_set_rate(&sc->sc_clks[A64_CLK_PLL_VIDEO0].base, 297000000);
645 clk_set_rate(&sc->sc_clks[A64_CLK_PLL_VIDEO1].base, 297000000);
648 clk_set_parent(&sc->sc_clks[A64_CLK_TCON1].base, &sc->sc_clks[A64_CLK_PLL_VIDEO1].base);
651 clk_set_parent(&sc->sc_clks[A64_CLK_HDMI].base, &sc->sc_clks[A64_CLK_PLL_VIDEO1].base)
[all...] |
| sunxi_ccu.c | 118 clk = &sc->sc_clks[clock_id];
296 if (sc->sc_clks[i].base.name == NULL)
298 if (strcmp(sc->sc_clks[i].base.name, name) == 0)
299 return &sc->sc_clks[i];
325 sc->sc_clks[i].base.domain = &sc->sc_clkdom;
326 clk_attach(&sc->sc_clks[i].base);
347 clk = &sc->sc_clks[i];
|
| sunxi_rtc.c | 299 struct clk sc_clks[SUNXI_RTC_NCLKS]; member in struct:sunxi_rtc_softc
349 return &sc->sc_clks[clock_id];
431 sc->sc_clks[i].domain = &sc->sc_clkdom;
432 sc->sc_clks[i].name = sc->sc_clk_names[i];
433 clk_attach(&sc->sc_clks[i]);
506 return &sc->sc_clks[i];
518 if (clk == &sc->sc_clks[SUNXI_RTC_CLK_IOSC]) {
548 if (clk != &sc->sc_clks[SUNXI_RTC_CLK_LOSC_GATE])
567 if (clk != &sc->sc_clks[SUNXI_RTC_CLK_LOSC_GATE])
586 if (clk == &sc->sc_clks[SUNXI_RTC_CLK_IOSC]
[all...] |
| sun8i_h3_r_ccu.c | 119 sc->sc_clks = sun8i_h3_r_ccu_clks;
|
| sun9i_a80_mmcclk.c | 93 sc->sc_clks = sun9i_a80_mmcclk_clks;
|
| sun50i_a64_r_ccu.c | 133 sc->sc_clks = sun50i_a64_r_ccu_clks;
|
| sun50i_h6_r_ccu.c | 148 sc->sc_clks = sun50i_h6_r_ccu_clks;
|
| sun9i_a80_usbclk.c | 131 sc->sc_clks = sun9i_a80_usbclk_clks;
|
| sunxi_de2_ccu.c | 139 sc->sc_clks = conf->clks;
|
| sun5i_a13_ccu.c | 311 sc->sc_clks = sun5i_a13_ccu_clks;
|
| sun6i_a31_ccu.c | 295 sc->sc_clks = sun6i_a31_ccu_clks;
|
| sun8i_v3s_ccu.c | 405 sc->sc_clks = sun8i_v3s_ccu_clks;
|
| /src/sys/arch/arm/amlogic/ |
| meson_clk.c | 119 clk = &sc->sc_clks[clock_id];
297 if (sc->sc_clks[i].base.name == NULL)
299 if (strcmp(sc->sc_clks[i].base.name, name) == 0)
300 return &sc->sc_clks[i];
315 sc->sc_clks[i].base.domain = &sc->sc_clkdom;
316 clk_attach(&sc->sc_clks[i].base);
337 clk = &sc->sc_clks[i];
|
| mesongxbb_aoclkc.c | 102 sc->sc_clks = mesongxbb_aoclkc_clks;
|
| mesong12_aoclkc.c | 127 sc->sc_clks = mesong12_aoclkc_clks;
|
| mesongxbb_clkc.c | 250 sc->sc_clks = mesongxbb_clkc_clks;
|
| meson8b_clkc.c | 349 sc->sc_clks = meson8b_clkc_clks;
|
| /src/sys/arch/arm/rockchip/ |
| rk_cru.c | 105 clk = &sc->sc_clks[i];
286 if (sc->sc_clks[i].base.name == NULL)
288 if (strcmp(sc->sc_clks[i].base.name, name) == 0)
289 return &sc->sc_clks[i];
324 sc->sc_clks[i].base.domain = &sc->sc_clkdom;
325 clk_attach(&sc->sc_clks[i].base);
346 clk = &sc->sc_clks[i];
|
| rk3288_cru.c | 351 sc->sc_clks = rk3288_cru_clks;
|
| /src/sys/arch/arm/ti/ |
| ti_prcm.c | 190 if (sc->sc_clks[i].base.name == NULL)
192 if (strcmp(sc->sc_clks[i].base.name, name) == 0)
193 return &sc->sc_clks[i];
218 sc->sc_clks[i].base.domain = &sc->sc_clkdom;
|
| am3_prcm.c | 237 struct ti_prcm_clk *tclk = &sc->sc_prcm.sc_clks[n];
277 sc->sc_prcm.sc_clks = am3_prcm_clks;
|
| ti_prcm.h | 165 struct ti_prcm_clk *sc_clks; member in struct:ti_prcm_softc
|
| omap3_cm.c | 200 sc->sc_clks = omap3_cm_clks;
|
