1 /* $NetBSD: imx8mq_ccm.c,v 1.2 2021/01/27 03:10:20 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 2020 Jared McNeill <jmcneill (at) invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 31 __KERNEL_RCSID(0, "$NetBSD: imx8mq_ccm.c,v 1.2 2021/01/27 03:10:20 thorpej Exp $"); 32 33 #include <sys/param.h> 34 #include <sys/bus.h> 35 #include <sys/device.h> 36 #include <sys/systm.h> 37 38 #include <dev/fdt/fdtvar.h> 39 40 #include <arm/nxp/imx_ccm.h> 41 #include <arm/nxp/imx8mq_ccm.h> 42 43 static int imx8mq_ccm_match(device_t, cfdata_t, void *); 44 static void imx8mq_ccm_attach(device_t, device_t, void *); 45 46 static const struct device_compatible_entry compat_data[] = { 47 { .compat = "fsl,imx8mq-ccm" }, 48 DEVICE_COMPAT_EOL 49 }; 50 51 static const char *uart_p[] = { 52 "osc_25m", "sys1_pll_80m", "sys2_pll_200m", "sys2_pll_100m", "sys3_pll_out", "clk_ext2", "clk_ext4", "audio_pll2_out" 53 }; 54 static const char *usdhc_p[] = { 55 "osc_25m", "sys1_pll_400m", "sys1_pll_800m", "sys2_pll_500m", "audio_pll2_out", "sys1_pll_266m", "sys3_pll_out", "sys1_pll_100m" 56 }; 57 static const char *enet_axi_p[] = { 58 "osc_25m", "sys1_pll_266m", "sys1_pll_800m", "sys2_pll_250m", "sys2_pll_200m", "audio_pll1_out", "video_pll1_out", "sys3_pll_out" 59 }; 60 static const char *enet_ref_p[] = { 61 "osc_25m", "sys2_pll_125m", "sys2_pll_500m", "sys2_pll_100m", "sys1_pll_160m", "audio_pll1_out", "video_pll1_out", "clk_ext4" 62 }; 63 static const char *enet_timer_p[] = { 64 "osc_25m", "sys2_pll_100m", "audio_pll1_out", "clk_ext1", "clk_ext2", "clk_ext3", "clk_ext4", "video_pll1_out" 65 }; 66 static const char *enet_phy_ref_p[] = { 67 "osc_25m", "sys2_pll_50m", "sys2_pll_125m", "sys2_pll_500m", "audio_pll1_out", "video_pll1_out", "audio_pll2_out" 68 }; 69 static const char *usb_bus_p[] = { 70 "osc_25m", "sys2_pll_500m", "sys1_pll_800m", "sys2_pll_100m", "sys2_pll_200m", "clk_ext2", "clk_ext4", "audio_pll2_out" 71 }; 72 static const char *usb_core_phy_p[] = { 73 "osc_25m", "sys1_pll_100m", "sys1_pll_40m", "sys2_pll_100m", "sys2_pll_200m", "clk_ext2", "clk_ext3", "audio_pll2_out" 74 }; 75 static const char *i2c_p[] = { 76 "osc_25m", "sys1_pll_160m", "sys2_pll_50m", "sys3_pll_out", "audio_pll1_out", "video_pll1_out", "audio_pll2_out", "sys1_pll_133m" 77 }; 78 79 CFATTACH_DECL_NEW(imx8mq_ccm, sizeof(struct imx_ccm_softc), 80 imx8mq_ccm_match, imx8mq_ccm_attach, NULL, NULL); 81 82 static struct imx_ccm_clk imx8mq_ccm_clks[] = { 83 84 IMX_FIXED(CLK_DUMMY, "dummy", 0), 85 IMX_EXTCLK(CLK_32K, "ckil"), 86 IMX_EXTCLK(CLK_25M, "osc_25m"), 87 IMX_EXTCLK(CLK_27M, "osc_27m"), 88 IMX_EXTCLK(CLK_EXT1, "clk_ext1"), 89 IMX_EXTCLK(CLK_EXT2, "clk_ext2"), 90 IMX_EXTCLK(CLK_EXT3, "clk_ext3"), 91 IMX_EXTCLK(CLK_EXT4, "clk_ext4"), 92 93 IMX_FIXED(SYS1_PLL_OUT, "sys1_pll_out", 800000000), 94 IMX_FIXED(SYS2_PLL_OUT, "sys2_pll_out", 1000000000), 95 96 IMX_GATE(SYS1_PLL_40M_CG, "sys1_pll_40m_cg", "sys1_pll_out", 0x30, __BIT(9)), 97 IMX_GATE(SYS1_PLL_80M_CG, "sys1_pll_80m_cg", "sys1_pll_out", 0x30, __BIT(11)), 98 IMX_GATE(SYS1_PLL_100M_CG, "sys1_pll_100m_cg", "sys1_pll_out", 0x30, __BIT(13)), 99 IMX_GATE(SYS1_PLL_133M_CG, "sys1_pll_133m_cg", "sys1_pll_out", 0x30, __BIT(15)), 100 IMX_GATE(SYS1_PLL_160M_CG, "sys1_pll_160m_cg", "sys1_pll_out", 0x30, __BIT(17)), 101 IMX_GATE(SYS1_PLL_200M_CG, "sys1_pll_200m_cg", "sys1_pll_out", 0x30, __BIT(19)), 102 IMX_GATE(SYS1_PLL_266M_CG, "sys1_pll_266m_cg", "sys1_pll_out", 0x30, __BIT(21)), 103 IMX_GATE(SYS1_PLL_400M_CG, "sys1_pll_400m_cg", "sys1_pll_out", 0x30, __BIT(23)), 104 IMX_GATE(SYS1_PLL_800M_CG, "sys1_pll_800m_cg", "sys1_pll_out", 0x30, __BIT(25)), 105 106 IMX_FIXED_FACTOR(SYS1_PLL_40M, "sys1_pll_40m", "sys1_pll_40m_cg", 1, 20), 107 IMX_FIXED_FACTOR(SYS1_PLL_80M, "sys1_pll_80m", "sys1_pll_80m_cg", 1, 10), 108 IMX_FIXED_FACTOR(SYS1_PLL_100M, "sys1_pll_100m", "sys1_pll_100m_cg", 1, 8), 109 IMX_FIXED_FACTOR(SYS1_PLL_133M, "sys1_pll_133m", "sys1_pll_133m_cg", 1, 6), 110 IMX_FIXED_FACTOR(SYS1_PLL_160M, "sys1_pll_160m", "sys1_pll_160m_cg", 1, 5), 111 IMX_FIXED_FACTOR(SYS1_PLL_200M, "sys1_pll_200m", "sys1_pll_200m_cg", 1, 4), 112 IMX_FIXED_FACTOR(SYS1_PLL_266M, "sys1_pll_266m", "sys1_pll_266m_cg", 1, 3), 113 IMX_FIXED_FACTOR(SYS1_PLL_400M, "sys1_pll_400m", "sys1_pll_400m_cg", 1, 2), 114 IMX_FIXED_FACTOR(SYS1_PLL_800M, "sys1_pll_800m", "sys1_pll_800m_cg", 1, 1), 115 116 IMX_GATE(SYS2_PLL_50M_CG, "sys2_pll_50m_cg", "sys2_pll_out", 0x3c, __BIT(9)), 117 IMX_GATE(SYS2_PLL_100M_CG, "sys2_pll_100m_cg", "sys2_pll_out", 0x3c, __BIT(11)), 118 IMX_GATE(SYS2_PLL_125M_CG, "sys2_pll_125m_cg", "sys2_pll_out", 0x3c, __BIT(13)), 119 IMX_GATE(SYS2_PLL_166M_CG, "sys2_pll_166m_cg", "sys2_pll_out", 0x3c, __BIT(15)), 120 IMX_GATE(SYS2_PLL_200M_CG, "sys2_pll_200m_cg", "sys2_pll_out", 0x3c, __BIT(17)), 121 IMX_GATE(SYS2_PLL_250M_CG, "sys2_pll_250m_cg", "sys2_pll_out", 0x3c, __BIT(19)), 122 IMX_GATE(SYS2_PLL_333M_CG, "sys2_pll_333m_cg", "sys2_pll_out", 0x3c, __BIT(21)), 123 IMX_GATE(SYS2_PLL_500M_CG, "sys2_pll_500m_cg", "sys2_pll_out", 0x3c, __BIT(23)), 124 IMX_GATE(SYS2_PLL_1000M_CG, "sys2_pll_1000m_cg", "sys2_pll_out", 0x3c, __BIT(25)), 125 126 IMX_FIXED_FACTOR(SYS2_PLL_50M, "sys2_pll_50m", "sys2_pll_50m_cg", 1, 20), 127 IMX_FIXED_FACTOR(SYS2_PLL_100M, "sys2_pll_100m", "sys2_pll_100m_cg", 1, 10), 128 IMX_FIXED_FACTOR(SYS2_PLL_125M, "sys2_pll_125m", "sys2_pll_125m_cg", 1, 8), 129 IMX_FIXED_FACTOR(SYS2_PLL_166M, "sys2_pll_166m", "sys2_pll_166m_cg", 1, 6), 130 IMX_FIXED_FACTOR(SYS2_PLL_200M, "sys2_pll_200m", "sys2_pll_200m_cg", 1, 5), 131 IMX_FIXED_FACTOR(SYS2_PLL_250M, "sys2_pll_250m", "sys2_pll_250m_cg", 1, 4), 132 IMX_FIXED_FACTOR(SYS2_PLL_333M, "sys2_pll_333m", "sys2_pll_333m_cg", 1, 3), 133 IMX_FIXED_FACTOR(SYS2_PLL_500M, "sys2_pll_500m", "sys2_pll_500m_cg", 1, 2), 134 IMX_FIXED_FACTOR(SYS2_PLL_1000M, "sys2_pll_1000m", "sys2_pll_1000m_cg", 1, 1), 135 136 IMX_COMPOSITE(CLK_UART1, "uart1", uart_p, 0xaf00, 0), 137 IMX_COMPOSITE(CLK_UART2, "uart2", uart_p, 0xaf80, 0), 138 IMX_COMPOSITE(CLK_UART3, "uart3", uart_p, 0xb000, 0), 139 IMX_COMPOSITE(CLK_UART4, "uart4", uart_p, 0xb080, 0), 140 141 IMX_ROOT_GATE(CLK_UART1_ROOT, "uart1_root_clk", "uart1", 0x4490), 142 IMX_ROOT_GATE(CLK_UART2_ROOT, "uart2_root_clk", "uart2", 0x44a0), 143 IMX_ROOT_GATE(CLK_UART3_ROOT, "uart3_root_clk", "uart3", 0x44b0), 144 IMX_ROOT_GATE(CLK_UART4_ROOT, "uart4_root_clk", "uart4", 0x44c0), 145 146 IMX_COMPOSITE(CLK_USDHC1, "usdhc1", usdhc_p, 0xac00, IMX_COMPOSITE_ROUND_DOWN), 147 IMX_COMPOSITE(CLK_USDHC2, "usdhc2", usdhc_p, 0xac80, IMX_COMPOSITE_ROUND_DOWN), 148 149 IMX_ROOT_GATE(CLK_USDHC1_ROOT, "usdhc1_root_clk", "usdhc1", 0x4510), 150 IMX_ROOT_GATE(CLK_USDHC2_ROOT, "usdhc2_root_clk", "usdhc2", 0x4520), 151 152 IMX_COMPOSITE(CLK_ENET_AXI, "enet_axi", enet_axi_p, 0x8800, 0), 153 IMX_COMPOSITE(CLK_ENET_REF, "enet_ref", enet_ref_p, 0xa980, 0), 154 IMX_COMPOSITE(CLK_ENET_TIMER, "enet_timer", enet_timer_p, 0xaa00, 0), 155 IMX_COMPOSITE(CLK_ENET_PHY_REF, "enet_phy_ref", enet_phy_ref_p, 0xaa80, 0), 156 157 IMX_ROOT_GATE(CLK_ENET1_ROOT, "enet1_root_clk", "enet_axi", 0x40a0), 158 159 IMX_COMPOSITE(CLK_USB_BUS, "usb_bus", usb_bus_p, 0x8b80, 0), 160 IMX_COMPOSITE(CLK_USB_CORE_REF, "usb_core_ref", usb_core_phy_p, 0xb100, 0), 161 IMX_COMPOSITE(CLK_USB_PHY_REF, "usb_phy_ref", usb_core_phy_p, 0xb180, 0), 162 163 IMX_ROOT_GATE(CLK_USB1_CTRL_ROOT, "usb1_ctrl_root_clk", "usb_bus", 0x44d0), 164 IMX_ROOT_GATE(CLK_USB2_CTRL_ROOT, "usb2_ctrl_root_clk", "usb_bus", 0x44e0), 165 IMX_ROOT_GATE(CLK_USB1_PHY_ROOT, "usb1_phy_root_clk", "usb_phy_ref", 0x44f0), 166 IMX_ROOT_GATE(CLK_USB2_PHY_ROOT, "usb2_phy_root_clk", "usb_phy_ref", 0x4500), 167 168 IMX_COMPOSITE(CLK_I2C1, "i2c1", i2c_p, 0xad00, 0), 169 IMX_COMPOSITE(CLK_I2C2, "i2c2", i2c_p, 0xad80, 0), 170 IMX_COMPOSITE(CLK_I2C3, "i2c3", i2c_p, 0xae00, 0), 171 IMX_COMPOSITE(CLK_I2C4, "i2c4", i2c_p, 0xae80, 0), 172 173 IMX_ROOT_GATE(CLK_I2C1_ROOT, "i2c1_root_clk", "i2c1", 0x4170), 174 IMX_ROOT_GATE(CLK_I2C2_ROOT, "i2c2_root_clk", "i2c2", 0x4180), 175 IMX_ROOT_GATE(CLK_I2C3_ROOT, "i2c3_root_clk", "i2c3", 0x4190), 176 IMX_ROOT_GATE(CLK_I2C4_ROOT, "i2c4_root_clk", "i2c4", 0x41a0), 177 }; 178 179 static int 180 imx8mq_ccm_match(device_t parent, cfdata_t cf, void *aux) 181 { 182 struct fdt_attach_args * const faa = aux; 183 184 return of_compatible_match(faa->faa_phandle, compat_data); 185 } 186 187 static void 188 imx8mq_ccm_attach(device_t parent, device_t self, void *aux) 189 { 190 struct imx_ccm_softc * const sc = device_private(self); 191 struct fdt_attach_args * const faa = aux; 192 193 sc->sc_dev = self; 194 sc->sc_phandle = faa->faa_phandle; 195 sc->sc_bst = faa->faa_bst; 196 197 sc->sc_clks = imx8mq_ccm_clks; 198 sc->sc_nclks = __arraycount(imx8mq_ccm_clks); 199 200 if (imx_ccm_attach(sc) != 0) 201 return; 202 203 aprint_naive("\n"); 204 aprint_normal(": Clock Control Module\n"); 205 206 imx_ccm_print(sc); 207 } 208
Indexes created Sat Sep 20 22:09:52 GMT 2025