| /src/sys/dev/clk/ |
| clk_backend.h | 55 int (*set_rate)(void *, struct clk *, u_int); member in struct:clk_funcs
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| clk.c | 237 if (clk->domain->funcs->set_rate)
238 return clk->domain->funcs->set_rate(clk->domain->priv,
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| /src/sys/arch/arm/nvidia/ |
| tegra_var.h | 73 u_int (*set_rate)(u_int); member in struct:tegra_cpufreq_func
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| tegra_cpufreq.c | 55 #define cpufreq_set_rate cpufreq_func->set_rate
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| tegra124_cpu.c | 79 .set_rate = tegra124_cpufreq_set_rate,
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| /src/sys/dev/ic/ |
| ac97var.h | 78 int (*set_rate)(struct ac97_codec_if *, int, u_int *); member in struct:ac97_codec_if_vtbl
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| /src/sys/arch/arm/amlogic/ |
| meson_clk.h | 151 .set_rate = meson_clk_div_set_rate, \
181 .set_rate = meson_clk_fixed_factor_set_rate, \
211 .set_rate = _setratefn, \
275 .set_rate = (_setratefn), \
349 int (*set_rate)(struct meson_clk_softc *, member in struct:meson_clk_clk
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| meson_clk.c | 183 if (clk->set_rate)
184 return clk->set_rate(sc, clk, rate);
285 .set_rate = meson_clk_clock_set_rate,
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| /src/sys/arch/arm/nxp/ |
| imx_ccm.h | 70 .set_rate = imx_ccm_extclk_set_rate, \
140 .set_rate = imx_ccm_composite_set_rate, \
219 .set_rate = imx_ccm_fixed_factor_set_rate, \
282 .set_rate = imx_ccm_div_set_rate, \
310 int (*set_rate)(struct imx_ccm_softc *, member in struct:imx_ccm_clk
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| imx_ccm.c | 120 if (clk->set_rate)
121 return clk->set_rate(sc, clk, rate);
222 .set_rate = imx_ccm_clock_set_rate,
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| /src/sys/arch/arm/sunxi/ |
| sunxi_ccu.h | 146 .set_rate = sunxi_ccu_nkmp_set_rate, \
197 .set_rate = sunxi_ccu_nm_set_rate, \
247 .set_rate = sunxi_ccu_div_set_rate, \
308 .set_rate = sunxi_ccu_prediv_set_rate, \
334 .set_rate = sunxi_ccu_phase_set_rate, \
360 .set_rate = sunxi_ccu_fixed_factor_set_rate, \
412 .set_rate = sunxi_ccu_fractional_set_rate, \
465 int (*set_rate)(struct sunxi_ccu_softc *, member in struct:sunxi_ccu_clk
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| sunxi_ccu.c | 182 if (clk->set_rate)
183 return clk->set_rate(sc, clk, rate);
284 .set_rate = sunxi_ccu_clock_set_rate,
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| sun4i_a10_ccu.c | 428 .set_rate = sun4i_a10_ccu_lcd0ch0_set_rate,
445 .set_rate = sun4i_a10_ccu_lcd1ch0_set_rate,
462 .set_rate = sun4i_a10_ccu_lcd0ch1_set_rate,
478 .set_rate = sun4i_a10_ccu_lcd1ch1_set_rate,
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| sun8i_a23_apbclk.c | 62 .set_rate = sun8i_a23_apbclk_set_rate,
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| sun9i_a80_cpusclk.c | 65 .set_rate = sun9i_a80_cpusclk_set_rate,
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| sun8i_a83t_ccu.c | 192 .set_rate = sun8i_a83t_ccu_cpux_set_rate,
213 .set_rate = sun8i_a83t_ccu_cpux_set_rate,
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| sun9i_a80_ccu.c | 194 .set_rate = sun9i_a80_ccu_cpux_set_rate,
215 .set_rate = sun9i_a80_ccu_cpux_set_rate,
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| sunxi_gmacclk.c | 68 .set_rate = sunxi_gmacclk_set_rate,
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| /src/sys/arch/arm/ti/ |
| ti_prcm.c | 99 if (clk->set_rate)
100 return clk->set_rate(sc, clk, rate);
179 .set_rate = ti_prcm_clock_set_rate,
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| ti_prcm.h | 78 int (*set_rate)(struct ti_prcm_softc *, member in struct:ti_prcm_clk
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| ti_dpll_clock.c | 81 .set_rate = am3_dpll_clock_set_rate,
91 .set_rate = omap3_dpll_clock_set_rate,
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| /src/sys/arch/arm/rockchip/ |
| rk_cru.c | 172 if (clk->set_rate)
173 return clk->set_rate(sc, clk, rate);
274 .set_rate = rk_cru_clock_set_rate,
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| rk_cru.h | 127 .set_rate = rk_cru_pll_set_rate, \
207 .set_rate = rk_cru_arm_set_rate, \
227 .set_rate = rk_cru_arm_set_rate, \
316 .set_rate = rk_cru_composite_set_rate, \
430 int (*set_rate)(struct rk_cru_softc *, member in struct:rk_cru_clk
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| /src/sys/dev/pci/ |
| auacer.c | 506 return sc->codec_if->vtbl->set_rate(sc->codec_if,
508 ret = sc->codec_if->vtbl->set_rate(sc->codec_if,
513 ret = sc->codec_if->vtbl->set_rate(sc->codec_if,
518 ret = sc->codec_if->vtbl->set_rate(sc->codec_if,
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| /src/sys/arch/arm/xscale/ |
| pxa2x0_ac97.c | 530 (void) sc->sc_codec_if->vtbl->set_rate(sc->sc_codec_if,
533 (void) sc->sc_codec_if->vtbl->set_rate(sc->sc_codec_if,
572 err = sc->sc_codec_if->vtbl->set_rate(sc->sc_codec_if,
580 err = sc->sc_codec_if->vtbl->set_rate(sc->sc_codec_if,
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