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    Searched refs:spll_func_cntl_2 (Results 1 - 12 of 12) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/radeon/
radeon_rv740_dpm.c 131 u32 spll_func_cntl_2 = pi->clk_regs.rv770.cg_spll_func_cntl_2; local
156 spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK;
157 spll_func_cntl_2 |= SCLK_MUX_SEL(2);
183 sclk->vCG_SPLL_FUNC_CNTL_2 = cpu_to_be32(spll_func_cntl_2);
328 u32 spll_func_cntl_2 = pi->clk_regs.rv770.cg_spll_func_cntl_2; local
375 spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK;
376 spll_func_cntl_2 |= SCLK_MUX_SEL(4);
388 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_2 = cpu_to_be32(spll_func_cntl_2);
radeon_rv730_dpm.c 51 u32 spll_func_cntl_2 = pi->clk_regs.rv730.cg_spll_func_cntl_2; local
88 spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK;
89 spll_func_cntl_2 |= SCLK_MUX_SEL(2);
115 sclk->vCG_SPLL_FUNC_CNTL_2 = cpu_to_be32(spll_func_cntl_2);
243 u32 spll_func_cntl_2; local
292 spll_func_cntl_2 = pi->clk_regs.rv730.cg_spll_func_cntl_2;
298 spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK;
299 spll_func_cntl_2 |= SCLK_MUX_SEL(4);
310 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_2 = cpu_to_be32(spll_func_cntl_2);
radeon_rv770_dpm.c 496 u32 spll_func_cntl_2 = local
535 spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK;
536 spll_func_cntl_2 |= SCLK_MUX_SEL(2);
562 sclk->vCG_SPLL_FUNC_CNTL_2 = cpu_to_be32(spll_func_cntl_2);
934 u32 spll_func_cntl_2 = local
983 spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK;
984 spll_func_cntl_2 |= SCLK_MUX_SEL(4);
997 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_2 = cpu_to_be32(spll_func_cntl_2);
radeon_cypress_dpm.c 1351 u32 spll_func_cntl_2 = local
1436 spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK;
1437 spll_func_cntl_2 |= SCLK_MUX_SEL(4);
1456 cpu_to_be32(spll_func_cntl_2);
radeon_ni_dpm.c 1807 u32 spll_func_cntl_2 = ni_pi->clock_registers.cg_spll_func_cntl_2; local
1906 spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK;
1907 spll_func_cntl_2 |= SCLK_MUX_SEL(4);
1919 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_2 = cpu_to_be32(spll_func_cntl_2);
2010 u32 spll_func_cntl_2 = ni_pi->clock_registers.cg_spll_func_cntl_2; local
2037 spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK;
2038 spll_func_cntl_2 |= SCLK_MUX_SEL(2);
2064 sclk->vCG_SPLL_FUNC_CNTL_2 = spll_func_cntl_2;
radeon_si_dpm.c 4499 u32 spll_func_cntl_2 = si_pi->clock_registers.cg_spll_func_cntl_2; local
4579 spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK;
4580 spll_func_cntl_2 |= SCLK_MUX_SEL(4);
4604 cpu_to_be32(spll_func_cntl_2);
4793 u32 spll_func_cntl_2 = si_pi->clock_registers.cg_spll_func_cntl_2; local
4819 spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK;
4820 spll_func_cntl_2 |= SCLK_MUX_SEL(2);
4846 sclk->vCG_SPLL_FUNC_CNTL_2 = spll_func_cntl_2;
radeon_ci_dpm.c 3002 u32 spll_func_cntl_2 = pi->clock_registers.cg_spll_func_cntl_2; local
3031 spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK;
3032 spll_func_cntl_2 |= SCLK_MUX_SEL(4);
3035 table->ACPILevel.CgSpllFuncCntl2 = spll_func_cntl_2;
  /src/sys/external/bsd/drm2/dist/drm/amd/powerplay/smumgr/
amdgpu_fiji_smumgr.c 1315 uint32_t spll_func_cntl_2 = data->clock_registers.vCG_SPLL_FUNC_CNTL_2; local
1354 spll_func_cntl_2 = PHM_SET_FIELD(spll_func_cntl_2, CG_SPLL_FUNC_CNTL_2,
1358 table->ACPILevel.CgSpllFuncCntl2 = spll_func_cntl_2;
amdgpu_iceland_smumgr.c 1437 uint32_t spll_func_cntl_2 = data->clock_registers.vCG_SPLL_FUNC_CNTL_2; local
1470 spll_func_cntl_2 = PHM_SET_FIELD(spll_func_cntl_2,
1474 table->ACPILevel.CgSpllFuncCntl2 = spll_func_cntl_2;
amdgpu_ci_smumgr.c 1389 uint32_t spll_func_cntl_2 = data->clock_registers.vCG_SPLL_FUNC_CNTL_2; local
1422 spll_func_cntl_2 = PHM_SET_FIELD(spll_func_cntl_2,
1426 table->ACPILevel.CgSpllFuncCntl2 = spll_func_cntl_2;
amdgpu_tonga_smumgr.c 1189 uint32_t spll_func_cntl_2 = data->clock_registers.vCG_SPLL_FUNC_CNTL_2; local
1219 spll_func_cntl_2 = PHM_SET_FIELD(spll_func_cntl_2, CG_SPLL_FUNC_CNTL_2,
1223 table->ACPILevel.CgSpllFuncCntl2 = spll_func_cntl_2;
  /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_si_dpm.c 4963 u32 spll_func_cntl_2 = si_pi->clock_registers.cg_spll_func_cntl_2; local
5044 spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK;
5045 spll_func_cntl_2 |= SCLK_MUX_SEL(4);
5069 cpu_to_be32(spll_func_cntl_2);
5257 u32 spll_func_cntl_2 = si_pi->clock_registers.cg_spll_func_cntl_2; local
5283 spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK;
5284 spll_func_cntl_2 |= SCLK_MUX_SEL(2);
5310 sclk->vCG_SPLL_FUNC_CNTL_2 = spll_func_cntl_2;

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