| /src/sys/dev/pci/cxgb/ |
| cxgb_mc5.c | 101 t3_write_reg(adapter, A_MC5_DB_DBGI_REQ_CMD, cmd);
108 t3_write_reg(adapter, A_MC5_DB_DBGI_REQ_ADDR0, v1);
109 t3_write_reg(adapter, A_MC5_DB_DBGI_REQ_ADDR1, v2);
110 t3_write_reg(adapter, A_MC5_DB_DBGI_REQ_ADDR2, v3);
115 t3_write_reg(adapter, A_MC5_DB_DBGI_REQ_DATA0, v1);
116 t3_write_reg(adapter, A_MC5_DB_DBGI_REQ_DATA1, v2);
117 t3_write_reg(adapter, A_MC5_DB_DBGI_REQ_DATA2, v3);
134 t3_write_reg(adapter, A_MC5_DB_DBGI_REQ_ADDR0, addr_lo);
196 t3_write_reg(adap, A_MC5_DB_RSP_LATENCY,
198 t3_write_reg(adap, A_MC5_DB_PART_ID_INDEX, 2)
[all...] |
| cxgb_t3_hw.c | 91 t3_write_reg(adapter, p->reg_addr + offset, p->val);
110 t3_write_reg(adapter, addr, v | val);
131 t3_write_reg(adap, addr_reg, start_idx);
168 t3_write_reg(adap, mc7->offset + A_MC7_BD_ADDR,
170 t3_write_reg(adap, mc7->offset + A_MC7_BD_OP, 0);
206 t3_write_reg(adap, A_MI1_CFG, val);
224 t3_write_reg(adapter, A_MI1_ADDR, addr);
225 t3_write_reg(adapter, A_MI1_OP, V_MDI_OP(2));
243 t3_write_reg(adapter, A_MI1_ADDR, addr);
244 t3_write_reg(adapter, A_MI1_DATA, val)
[all...] |
| cxgb_xgmac.c | 65 t3_write_reg(adap, ctrl, adap->params.vpd.xauicfg[macidx(mac)] |
110 t3_write_reg(adap, A_XGM_RESET_CTRL + oft, F_MAC_RESET_);
137 t3_write_reg(adap, A_XGM_RX_MAX_PKT_SIZE + oft,
146 t3_write_reg(adap, A_XGM_TX_CTRL + oft, F_TXEN);
147 t3_write_reg(adap, A_XGM_RX_CTRL + oft, F_RXEN);
157 t3_write_reg(adap, A_XGM_RESET_CTRL + oft, val);
182 t3_write_reg(adap, A_XGM_RESET_CTRL + oft, F_MAC_RESET_);
195 t3_write_reg(adap, A_XGM_RESET_CTRL + oft, 0); /*MAC in reset*/
205 t3_write_reg(adap, A_XGM_RESET_CTRL + oft, val);
211 t3_write_reg(adap, A_XGM_RX_CFG + oft
[all...] |
| cxgb_sge.c | 244 t3_write_reg(adap, A_SG_CONTROL, ctrl);
245 t3_write_reg(adap, A_SG_EGR_RCQ_DRB_THRSH, V_HIRCQDRBTHRSH(512) |
247 t3_write_reg(adap, A_SG_TIMER_TICK, core_ticks_per_usec(adap) / 10);
248 t3_write_reg(adap, A_SG_CMDQ_CREDIT_TH, V_THRESHOLD(32) |
250 t3_write_reg(adap, A_SG_HI_DRB_HI_THRSH, 1000);
251 t3_write_reg(adap, A_SG_HI_DRB_LO_THRSH, 256);
252 t3_write_reg(adap, A_SG_LO_DRB_HI_THRSH, 1000);
253 t3_write_reg(adap, A_SG_LO_DRB_LO_THRSH, 256);
254 t3_write_reg(adap, A_SG_OCO_BASE, V_BASE1(0xfff));
255 t3_write_reg(adap, A_SG_DRB_PRI_THRESH, 63 * 1024)
[all...] |
| cxgb_main.c | 826 t3_write_reg(sc, A_XGM_TX_CTRL, 0);
827 t3_write_reg(sc, A_XGM_RX_CTRL, 0);
828 t3_write_reg(sc, XGM_REG(A_XGM_TX_CTRL, 1), 0);
829 t3_write_reg(sc, XGM_REG(A_XGM_RX_CTRL, 1), 0);
940 t3_write_reg(sc, A_PL_INT_ENABLE0, sc->slow_intr_mask);
1109 t3_write_reg(sc, A_ULPRX_TDDP_PSZ, V_HPZ0(PAGE_SHIFT - 12));
1573 t3_write_reg(sc, A_PL_INT_CAUSE0, F_T3DBG);
1574 t3_write_reg(sc, A_PL_INT_ENABLE0, sc->slow_intr_mask);
|
| cxgb_offload.c | 222 t3_write_reg(adapter, A_XGM_TX_CTRL + mac->offset,
227 t3_write_reg(adapter, A_XGM_RX_CTRL + mac->offset, 0);
229 t3_write_reg(adapter, A_XGM_RX_CTRL + mac->offset,
261 t3_write_reg(adapter, A_ULPRX_ISCSI_TAGMASK, uiip->tagmask);
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| cxgb_adapter.h | 439 t3_write_reg(adapter_t *adapter, uint32_t reg_addr, uint32_t val) function in typeref:typename:void
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