| /src/sys/arch/evbmips/ingenic/ |
| clock.c | 78 writereg(JZ_TC_TFCR, TFR_OSTFLAG);
79 writereg(JZ_OST_DATA, ci->ci_next_cp0_clk_intr);
97 writereg(JZ_TC_TMCR, TFR_OSTFLAG);
99 writereg(JZ_TC_TECR, TESR_TCST5); /* disable timer 5 */
100 writereg(JZ_TC_TCNT(5), 0);
101 writereg(JZ_TC_TDFR(5), 30000); /* 10ms at 48MHz / 16 */
102 writereg(JZ_TC_TDHR(5), 60000); /* not reached */
103 writereg(JZ_TC_TCSR(5), TCSR_EXT_EN| TCSR_DIV_16);
104 writereg(JZ_TC_TMCR, TFR_FFLAG5);
105 writereg(JZ_TC_TFCR, TFR_FFLAG5)
[all...] |
| machdep.c | 113 writereg(JZ_TC_TECR, TESR_OST);
115 writereg(JZ_OST_CTRL, 0);
116 writereg(JZ_OST_CNT_LO, 0);
117 writereg(JZ_OST_CNT_HI, 0);
118 writereg(JZ_OST_DATA, 0xffffffff);
120 writereg(JZ_OST_CTRL, OSTC_EXT_EN | OSTC_MODE | OSTC_DIV_4);
122 writereg(JZ_TC_TESR, TESR_OST);
347 writereg(JZ_WDOG_TCER, 0); /* disable watchdog */
348 writereg(JZ_WDOG_TCNT, 0); /* reset counter */
349 writereg(JZ_WDOG_TDR, 128); /* wait for ~1s *
[all...] |
| intr.c | 127 writereg(JZ_ICMR0, 0xffffffff);
128 writereg(JZ_ICMR1, 0xffffffff);
234 writereg(JZ_ICMSR0, 0x0c000000);
236 writereg(JZ_ICMCR0, 0x0c000000);
264 writereg(JZ_ICMSR0, ll);
265 writereg(JZ_ICMSR1, hh);
279 writereg(JZ_ICMSR0, mask);
307 writereg(JZ_ICMSR1, mask);
312 writereg(JZ_ICMCR0, ll);
313 writereg(JZ_ICMCR1, hh)
[all...] |
| /src/sys/arch/mips/ingenic/ |
| ingenic_ehci.c | 91 writereg(JZ_USBPCR, reg);
96 writereg(JZ_USBPCR1, reg);
102 writereg(JZ_USBPCR1, reg);
107 writereg(JZ_OPCR, reg);
112 writereg(JZ_USBPCR1, reg);
117 writereg(JZ_USBPCR1, reg);
122 writereg(JZ_USBPCR1, reg);
127 writereg(JZ_USBPCR, reg);
131 writereg(JZ_USBPCR, reg);
136 writereg(JZ_SRBC, reg)
[all...] |
| ingenic_dwctwo.c | 153 writereg(JZ_USBPCR, reg);
169 writereg(JZ_USBPCR1, reg);
175 writereg(JZ_USBVBFIL, 0);
180 writereg(JZ_USBPCR, reg);
183 writereg(JZ_USBPCR, reg);
190 writereg(JZ_OPCR, reg);
|
| ingenic_regs.h | 119 writereg(uint32_t reg, uint32_t val) function in typeref:typename:void
404 writereg(reg + JZ_GPIO_INTC, mask); /* use as gpio */
405 writereg(reg + JZ_GPIO_MASKS, mask);
406 writereg(reg + JZ_GPIO_PAT1C, mask); /* make output */
416 writereg(reg, mask);
425 writereg(reg + JZ_GPIO_INTC, mask); /* use as gpio */
426 writereg(reg + JZ_GPIO_MASKC, mask); /* device mode */
427 writereg(reg + JZ_GPIO_PAT1C, mask); /* select 0 */
428 writereg(reg + JZ_GPIO_PAT0C, mask);
437 writereg(reg + JZ_GPIO_INTC, mask); /* use as gpio *
[all...] |
| apbus.c | 163 writereg(JZ_CLKGR1, reg);
166 writereg(JZ_ERNG, 1);
171 writereg(JZ_OPCR, reg);
259 writereg(JZ_CLKGR0, reg);
265 writereg(JZ_CLKGR1, reg);
|
| ingenic_dme.c | 171 writereg(JZ_GPIO_E_BASE + JZ_GPIO_FLAGC, GPIO_DME_INT_MASK);
|
| /src/sys/arch/sgimips/dev/ |
| dpclock.c | 94 writereg(struct dpclock_softc *sc, uint32_t reg, uint8_t val) function in typeref:typename:void
154 writereg(sc, DP8573A_TIMESAVE_CTL, j);
155 writereg(sc, DP8573A_TIMESAVE_CTL, i);
204 writereg(sc, DP8573A_TIMESAVE_CTL, j);
205 writereg(sc, DP8573A_TIMESAVE_CTL, i);
223 writereg(sc, DP8573A_RT_MODE, j);
226 writereg(sc, DP8573A_COUNTERS +i, regs[DP8573A_COUNTERS + i]);
228 writereg(sc, DP8573A_RT_MODE, i);
|
