HomeSort by: relevance | last modified time | path
    Searched refs:x112 (Results 1 - 25 of 32) sorted by relevancy

1 2

  /src/sys/arch/powerpc/include/
spr.h 138 #define SPR_SPRG2 0x112 /* E468 SPR General 2 */
  /src/sys/arch/amiga/amiga/
cc_registers.h 163 #define R_BPL1DAT 0x112
  /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
ppsmc.h 185 #define PPSMC_MSG_DPM_N_LevelsDisabled ((uint32_t) 0x112)
  /src/sys/external/bsd/drm2/dist/drm/radeon/
ppsmc.h 181 #define PPSMC_MSG_DPM_N_LevelsDisabled ((uint32_t) 0x112)
r500_reg.h 211 #define RS600_MC_PT0_SYSTEM_APERTURE_LOW_ADDR 0x112
  /src/sys/arch/hpcmips/dev/
ite8181reg.h 93 #define ITE8181_GUI_CC0R2 0x112
  /src/lib/libform/
form.h 103 #define REQ_PREV_CHAR (KEY_MAX + 0x112) /* move to the previous
  /src/sys/arch/powerpc/include/ibm4xx/
dcr4xx.h 114 #define DCR_DMA0_DA2 0x112 /* DMA Destination Address Register 2 */
  /src/sys/external/bsd/drm2/dist/drm/amd/powerplay/inc/
fiji_ppsmc.h 197 #define PPSMC_MSG_DPM_N_LevelsDisabled ((uint16_t) 0x112)
smu7_ppsmc.h 194 #define PPSMC_MSG_DPM_N_LevelsDisabled ((uint16_t) 0x112)
tonga_ppsmc.h 218 #define PPSMC_MSG_DPM_N_LevelsDisabled ((uint16_t) 0x112)
  /src/sys/external/gpl2/dts/dist/include/dt-bindings/input/
linux-event-codes.h 359 #define BTN_MIDDLE 0x112
  /src/sys/arch/powerpc/powerpc/
db_disasm.c 438 { 0x112, "sprg2" },
570 { 0x112, "dma0_da2" },
  /src/sys/external/gpl2/dts/dist/arch/arm/boot/dts/
motorola-mapphone-common.dtsi 565 OMAP4_IOPAD(0x112, PIN_OUTPUT_PULLUP | MUX_MODE5) /* uart4_rts */
omap4-sdp.dts 252 OMAP4_IOPAD(0x112, PIN_INPUT | MUX_MODE0) /* abe_dmic_din1.abe_dmic_din1 */
  /src/sys/external/bsd/drm2/dist/include/drm/
drm_dp_helper.h 509 #define DP_AUDIO_DELAY0 0x112 /* 1.2 */
  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/bif/
bif_5_0_d.h 420 #define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB 0x112
  /src/sys/dev/qbus/
qfont.c 97 ,0x00 ,0x00 ,0x112 ,0x113 ,0x114 ,0x115 ,0x116 ,0x117 /* 136 */
132 ,0x00 ,0x00 ,0x112 ,0x113 ,0x114 ,0x115 ,0x116 ,0x117 /* 136 */
  /src/sys/external/bsd/drm/dist/shared-core/
radeon_drv.h 719 #define RS600_MC_PT0_SYSTEM_APERTURE_LOW_ADDR 0x112
  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gca/
gfx_8_0_enum.h 402 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_2TO2__1BLOCK_2TO1__1BLOCK_2TO2= 0x112,
1602 SC_PKR_DBHANG_FORCE_EOV = 0x112,
2559 SQ_PERF_SEL_ATC_INSTS_VMEM = 0x112,
3564 #define SQ_DPP_ROW_SR2 0x112
gfx_8_1_enum.h 402 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_2TO2__1BLOCK_2TO1__1BLOCK_2TO2= 0x112,
1620 SC_PKR_DBHANG_FORCE_EOV = 0x112,
2577 SQ_PERF_SEL_ATC_INSTS_VMEM = 0x112,
3582 #define SQ_DPP_ROW_SR2 0x112
  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gmc/
gmc_7_1_d.h 1175 #define ixMC_IO_DEBUG_DQB1L_RXPHASE_D1 0x112
gmc_8_1_d.h 1279 #define ixMC_IO_DEBUG_DQB1L_RXPHASE_D1 0x112
  /src/sys/arch/shark/shark/
sequoia.h 2987 ** SEQUOIA-1 Pin Select Register 3 (SEQPSR3) - Index 0x112
3005 #define SEQR_SEQPSR3_REG 0x112
  /src/sys/dev/ic/
ispmbox.h 1442 #define SNS_GPN_ID 0x112

Completed in 76 milliseconds

1 2