| /src/sys/arch/amiga/amiga/ |
| cc_registers.h | 171 #define R_SPR0PTL 0x122
|
| /src/sys/arch/hpcmips/dev/ |
| ite8181reg.h | 105 #define ITE8181_GUI_C1YC0 0x122 /* cursor 1 Y coord bits[7:0] */
|
| /src/sys/arch/alpha/alpha/ |
| db_disasm.c | 537 { "mult/uc", 0x122},
699 { "mulg/uc", 0x122},
|
| /src/sys/arch/alpha/include/ |
| alpha_instruction.h | 512 #define op_mult_uc 0x122
676 #define op_mulg_uc 0x122
|
| /src/sys/external/bsd/drm2/dist/drm/amd/powerplay/inc/ |
| tonga_ppsmc.h | 232 #define PPSMC_MSG_PCIE_PHYPowerDown ((uint16_t) 0x122)
235 #define PPSMC_MSG_Spmi_Enable ((uint16_t) 0x122)
|
| fiji_ppsmc.h | 211 #define PPSMC_MSG_Spmi_Enable ((uint16_t) 0x122)
|
| smu7_ppsmc.h | 208 #define PPSMC_MSG_Spmi_Enable ((uint16_t) 0x122)
|
| /src/lib/libform/ |
| form.h | 131 #define REQ_DEL_CHAR (KEY_MAX + 0x122) /* delete the current character */
|
| /src/sys/arch/x86/include/ |
| specialreg.h | 1255 #define MSR_IA32_TSX_CTRL 0x122
|
| /src/sys/external/gpl2/dts/dist/include/dt-bindings/input/ |
| linux-event-codes.h | 370 #define BTN_THUMB2 0x122
|
| /src/external/bsd/openldap/dist/libraries/libldap/ |
| t61.c | 269 0, 0, 0, 0xc7, 0x1e10, 0x228, 0, 0x122,
|
| /src/external/gpl3/binutils/dist/opcodes/ |
| sparc-opc.c | 2193 { "fpcmpune8", F3F(2, 0x36, 0x122), F3F(~2, ~0x36, ~0x122), "v,B,d", 0, HWCAP_VIS3, HWCAP2_VIS3B, v9d },
2194 { "fpcmpne8", F3F(2, 0x36, 0x122), F3F(~2, ~0x36, ~0x122), "v,B,d", F_PREF_ALIAS, HWCAP_VIS3, 0, v9d },
2195 { "fucmpne8", F3F(2, 0x36, 0x122), F3F(~2, ~0x36, ~0x122), "v,B,d", F_ALIAS, HWCAP_VIS3, 0, v9d },
|
| alpha-opc.c | 758 { "mulg/uc", FP(0x15,0x122), BASE, ARG_FP },
889 { "mult/uc", FP(0x16,0x122), BASE, ARG_FP },
|
| /src/external/gpl3/binutils.old/dist/opcodes/ |
| sparc-opc.c | 2193 { "fpcmpune8", F3F(2, 0x36, 0x122), F3F(~2, ~0x36, ~0x122), "v,B,d", 0, HWCAP_VIS3, HWCAP2_VIS3B, v9d },
2194 { "fpcmpne8", F3F(2, 0x36, 0x122), F3F(~2, ~0x36, ~0x122), "v,B,d", F_PREF_ALIAS, HWCAP_VIS3, 0, v9d },
2195 { "fucmpne8", F3F(2, 0x36, 0x122), F3F(~2, ~0x36, ~0x122), "v,B,d", F_ALIAS, HWCAP_VIS3, 0, v9d },
|
| alpha-opc.c | 758 { "mulg/uc", FP(0x15,0x122), BASE, ARG_FP },
889 { "mult/uc", FP(0x16,0x122), BASE, ARG_FP },
|
| /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/bif/ |
| bif_5_0_d.h | 436 #define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_MMIO_MAP_RANGE5 0x122
|
| /src/sys/dev/qbus/ |
| qfont.c | 98 ,0x00 ,0x00 ,0x120 ,0x00 ,0x121 ,0x122 ,0x123 ,0x124 /* 144 */
133 ,0x00 ,0x00 ,0x120 ,0x00 ,0x121 ,0x122 ,0x123 ,0x124 /* 144 */
|
| /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gca/ |
| gfx_8_0_enum.h | 418 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__1BLOCK_4TO1= 0x122,
1618 SC_PS_ARB_SC_BUSY = 0x122,
2575 SQ_PERF_SEL_ATC_INSTS_VMEM_REPLAY = 0x122,
3579 #define SQ_DPP_ROW_RR2 0x122
|
| gfx_8_1_enum.h | 418 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__1BLOCK_4TO1= 0x122,
1636 SC_PS_ARB_SC_BUSY = 0x122,
2593 SQ_PERF_SEL_ATC_INSTS_VMEM_REPLAY = 0x122,
3597 #define SQ_DPP_ROW_RR2 0x122
|
| /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gmc/ |
| gmc_7_1_d.h | 1191 #define ixMC_IO_DEBUG_DQB1L_TXPHASE_D0 0x122
|
| gmc_8_1_d.h | 1295 #define ixMC_IO_DEBUG_DQB1L_TXPHASE_D0 0x122
|
| /src/sys/dev/microcode/aic7xxx/ |
| aic79xx_reg.h | 1965 ahd_print_register(NULL, 0, "WAITING_TID_TAIL", 0x122, regvalue, cur_col, wrap)
3517 #define WAITING_TID_TAIL 0x122
|
| /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/ |
| amdgpu_si_dpm.c | 261 { 0x122, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
262 { 0x122, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
564 { 0x122, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
565 { 0x122, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
|
| /src/sys/external/bsd/drm2/dist/drm/ast/ |
| ast_post.c | 1456 param->dram_config = 0x122;
|
| /src/sys/external/bsd/drm2/dist/drm/radeon/ |
| radeon_si_dpm.c | 168 { 0x122, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
169 { 0x122, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
469 { 0x122, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
470 { 0x122, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
|
