| /src/sys/arch/sparc64/include/ |
| trap.h | 123 #define T_SETCC 0x133
|
| /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/ |
| ppsmc.h | 124 #define PPSMC_MSG_Thermal_Cntl_Disable ((uint16_t) 0x133)
|
| /src/sys/external/bsd/drm2/dist/drm/radeon/ |
| ppsmc.h | 121 #define PPSMC_MSG_Thermal_Cntl_Disable ((uint16_t) 0x133)
|
| /src/lib/libform/ |
| form.h | 158 #define REQ_SCR_HFLINE (KEY_MAX + 0x133) /* horizontal scroll
|
| /src/sys/arch/sparc64/sparc64/ |
| hvcall.S | 130 #define RNG_DATA_READ_DIAG 0x133
|
| locore.s | 821 STRAP(0x130); STRAP(0x131); STRAP(0x132); STRAP(0x133); STRAP(0x134); STRAP(0x135); STRAP(0x136); STRAP(0x137)
1032 STRAP(0x130); STRAP(0x131); STRAP(0x132); STRAP(0x133); STRAP(0x134); STRAP(0x135); STRAP(0x136); STRAP(0x137)
|
| /src/sys/external/bsd/drm2/dist/drm/amd/powerplay/inc/ |
| fiji_ppsmc.h | 229 #define PPSMC_MSG_Thermal_Cntl_Disable ((uint16_t) 0x133)
|
| smu7_ppsmc.h | 226 #define PPSMC_MSG_Thermal_Cntl_Disable ((uint16_t) 0x133)
|
| tonga_ppsmc.h | 253 #define PPSMC_MSG_Thermal_Cntl_Disable ((uint16_t) 0x133)
|
| /src/sys/external/gpl2/dts/dist/include/dt-bindings/input/ |
| linux-event-codes.h | 387 #define BTN_NORTH 0x133
|
| /src/sys/external/gpl2/dts/dist/arch/arm/boot/dts/ |
| qcom-apq8060-dragonboard.dts | 434 reg = <0x133>;
|
| /src/sys/dev/ic/ |
| rt2860reg.h | 1029 #define RT5390_EEPROM_IQ_GAIN_CAL_TX1_2GHZ 0x133
|
| /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gmc/ |
| gmc_7_1_d.h | 1208 #define ixMC_IO_DEBUG_DQB1H_TXPHASE_D1 0x133
|
| gmc_8_1_d.h | 1312 #define ixMC_IO_DEBUG_DQB1H_TXPHASE_D1 0x133
|
| /src/sys/dev/microcode/aic7xxx/ |
| aic79xx_reg.h | 2028 ahd_print_register(NULL, 0, "SEQ_FLAGS", 0x133, regvalue, cur_col, wrap)
3545 #define SEQ_FLAGS 0x133
|
| /src/sys/external/bsd/drm2/dist/drm/ast/ |
| ast_post.c | 1088 param->dram_config = 0x133;
|
| /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gca/ |
| gfx_8_0_enum.h | 435 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_2TO1__1BLOCK_4TO3= 0x133,
1635 SC_PA1_SC_EOP_WE = 0x133,
|
| gfx_8_1_enum.h | 435 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_2TO1__1BLOCK_4TO3= 0x133,
1653 SC_PA1_SC_EOP_WE = 0x133,
|
| gfx_7_2_enum.h | 1450 SC_PA1_SC_EOP_WE = 0x133,
|
| /src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/qcom/ |
| msm8996.dtsi | 663 reg = <0x133 0x1>;
|
| /src/sys/lib/libkern/arch/hppa/ |
| milli.S | 1349 x133: sh3add %r26,0,%r1 ! sh2add %r1,%r26,%r1 ! b e_t0 ! sh2add %r1,%r26,%r1 label
|
| /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/dce/ |
| dce_8_0_d.h | 1039 #define mmDCCG_PERFMON_CNTL 0x133
|
| dce_10_0_d.h | 1196 #define mmDCCG_PERFMON_CNTL 0x133
|
| dce_11_0_d.h | 1008 #define mmDCCG_PERFMON_CNTL 0x133
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| dce_11_2_d.h | 1082 #define mmDCCG_PERFMON_CNTL 0x133
|
