| /src/sys/external/gpl2/dts/dist/arch/arm/boot/dts/ |
| logicpd-torpedo-37xx-devkit.dts | 34 interrupts-extended = <&intc 94 &omap3_pmx_core 0x136>;
|
| omap4-var-om44customboard.dtsi | 76 OMAP4_IOPAD(0x136, PIN_INPUT | MUX_MODE0) /* mcspi1_simo.mcspi1_simo */
|
| logicpd-som-lv.dtsi | 128 interrupts-extended = <&intc 94 &omap3_pmx_core 0x136>;
|
| omap4-sdp.dts | 280 OMAP4_IOPAD(0x136, PIN_INPUT | MUX_MODE0) /* mcspi1_simo.mcspi1_simo */
|
| /src/sys/arch/amiga/amiga/ |
| cc_registers.h | 181 #define R_SPR5PTL 0x136
|
| /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/ |
| ppsmc.h | 126 #define PPSMC_MSG_PCIeDPM_Enable ((uint16_t) 0x136)
|
| amdgpu_cik.c | 221 0x136, 0x00000fff, 0x00000100,
486 0x136, 0x00000fff, 0x00000100,
740 0x136, 0x00000fff, 0x00000100,
|
| /src/sys/external/bsd/drm2/dist/drm/radeon/ |
| ppsmc.h | 123 #define PPSMC_MSG_PCIeDPM_Enable ((uint16_t) 0x136)
|
| /src/lib/libform/ |
| form.h | 164 #define REQ_SCR_HBHALF (KEY_MAX + 0x136) /* horizontal scroll
|
| /src/sys/arch/arm/nvidia/ |
| tegra210_xusbpad.c | 237 __SHIFTIN(0x136, XUSB_PADCTL_UPHY_PLL_P0_CTL_2_CAL_CTRL),
435 __SHIFTIN(0x136, XUSB_PADCTL_UPHY_PLL_S0_CTL_2_CAL_CTRL),
|
| /src/sys/external/bsd/drm2/dist/drm/amd/powerplay/inc/ |
| fiji_ppsmc.h | 232 #define PPSMC_MSG_PCIeDPM_Enable ((uint16_t) 0x136)
|
| smu7_ppsmc.h | 229 #define PPSMC_MSG_PCIeDPM_Enable ((uint16_t) 0x136)
|
| tonga_ppsmc.h | 256 #define PPSMC_MSG_PCIeDPM_Enable ((uint16_t) 0x136)
|
| /src/sys/external/gpl2/dts/dist/include/dt-bindings/input/ |
| linux-event-codes.h | 392 #define BTN_TL 0x136
|
| /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gmc/ |
| gmc_7_1_d.h | 1211 #define ixMC_IO_DEBUG_DQB3L_TXPHASE_D1 0x136
|
| gmc_8_1_d.h | 1315 #define ixMC_IO_DEBUG_DQB3L_TXPHASE_D1 0x136
|
| /src/sys/dev/microcode/aic7xxx/ |
| aic79xx_reg.h | 2049 ahd_print_register(NULL, 0, "LASTPHASE", 0x136, regvalue, cur_col, wrap)
3560 #define LASTPHASE 0x136
|
| /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gca/ |
| gfx_8_0_enum.h | 438 CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO2__1BLOCK_4TO2= 0x136,
1638 SC_PA2_SC_EOP_WE = 0x136,
|
| gfx_8_1_enum.h | 438 CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO2__1BLOCK_4TO2= 0x136,
1656 SC_PA2_SC_EOP_WE = 0x136,
|
| gfx_7_2_enum.h | 1453 SC_PA2_SC_EOP_WE = 0x136,
|
| /src/sys/lib/libkern/arch/hppa/ |
| milli.S | 1355 x136: sh3add %r26,0,%r1 ! sh1add %r1,%r26,%r1 ! b e_shift ! sh3add %r1,%r29,%r29 label
|
| /src/sys/external/bsd/drm2/dist/drm/nouveau/nvkm/engine/device/ |
| nouveau_nvkm_engine_device_base.c | 3195 case 0x136: device->chip = &nv136_chipset; break;
|
| /src/sys/arch/sparc64/sparc64/ |
| locore.s | 821 STRAP(0x130); STRAP(0x131); STRAP(0x132); STRAP(0x133); STRAP(0x134); STRAP(0x135); STRAP(0x136); STRAP(0x137)
1032 STRAP(0x130); STRAP(0x131); STRAP(0x132); STRAP(0x133); STRAP(0x134); STRAP(0x135); STRAP(0x136); STRAP(0x137)
|
| /src/sys/dev/microcode/bnx/ |
| bnxfw.h | 67 0x136, 0xea60, 0x5, 0x0,
3545 0x6000f00, 0x0, 0x136, 0xea60,
5236 0x6001100, 0x0, 0x136, 0xea60,
6570 0x136, 0xea60, 0x5, 0x0,
|
| /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/dce/ |
| dce_8_0_d.h | 1027 #define mmSCLK_CGTT_BLK_CTRL_REG 0x136
|
