| /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/ |
| ppsmc.h | 134 #define PPSMC_MSG_NBDPM_Disable ((uint16_t) 0x141)
|
| /src/sys/external/bsd/drm2/dist/drm/amd/powerplay/inc/ |
| cz_ppsmc.h | 143 #define PPSMC_MSG_NBDPM_Disable ((uint16_t) 0x141)
|
| fiji_ppsmc.h | 243 #define PPSMC_MSG_NBDPM_Disable ((uint16_t) 0x141)
|
| smu7_ppsmc.h | 240 #define PPSMC_MSG_NBDPM_Disable ((uint16_t) 0x141)
|
| tonga_ppsmc.h | 267 #define PPSMC_MSG_NBDPM_Disable ((uint16_t) 0x141)
|
| /src/sys/external/bsd/drm2/dist/drm/radeon/ |
| ppsmc.h | 131 #define PPSMC_MSG_NBDPM_Disable ((uint16_t) 0x141)
|
| /src/tests/net/route/ |
| t_route.sh | 253 flags: 0x141<UP,DONE,CONNECTED>
287 flags: 0x141<UP,DONE,CONNECTED>
327 flags: 0x141<UP,DONE,CONNECTED>
361 flags: 0x141<UP,DONE,CONNECTED>
|
| /src/external/gpl3/binutils/dist/gprofng/src/ |
| hwc_arm_ampere_1.h | 264 { I("msc_etm_extout0", 0x141, STXT("ETM extout bit 0")) },
|
| /src/external/gpl3/binutils.old/dist/gprofng/src/ |
| hwc_arm_ampere_1.h | 264 { I("msc_etm_extout0", 0x141, STXT("ETM extout bit 0")) },
|
| /src/sys/arch/alpha/alpha/ |
| db_disasm.c | 542 { "subs/um", 0x141},
|
| /src/sys/arch/alpha/include/ |
| alpha_instruction.h | 517 #define op_subs_um 0x141
|
| /src/sys/arch/riscv/include/ |
| insn.h | 730 #define CSR_SEPC 0x141
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
| SIDefines.h | 704 ROW_HALF_MIRROR = 0x141,
|
| /src/sys/external/gpl2/dts/dist/include/dt-bindings/input/ |
| linux-event-codes.h | 405 #define BTN_TOOL_RUBBER 0x141
|
| /src/external/bsd/openldap/dist/libraries/libldap/ |
| t61.c | 108 0x141, 0x0d8, 0x152, 0x0ba, 0x0de, 0x166, 0x14a, 0x149,
|
| /src/crypto/external/bsd/heimdal/dist/lib/hx509/ref/ |
| pkcs11.h | 624 #define CKM_CDMF_ECB (0x141)
|
| /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gmc/ |
| gmc_7_1_d.h | 1222 #define ixMC_IO_DEBUG_DQB0H_RX_VREF_CAL_D0 0x141
|
| gmc_8_1_d.h | 1326 #define ixMC_IO_DEBUG_DQB0H_RX_VREF_CAL_D0 0x141
|
| /src/sys/dev/microcode/aic7xxx/ |
| aic79xx_reg.h | 2084 ahd_print_register(NULL, 0, "TQINPOS", 0x141, regvalue, cur_col, wrap)
3583 #define TQINPOS 0x141
|
| /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gca/ |
| gfx_8_0_enum.h | 449 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO2__1BLOCK_2TO2= 0x141,
1649 SC_SC_PS_ENG_MULTICYCLE_BUBBLE = 0x141,
3598 #define SQ_DPP_ROW_HALF_MIRROR 0x141
|
| gfx_8_1_enum.h | 449 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO2__1BLOCK_2TO2= 0x141,
1667 SC_SC_PS_ENG_MULTICYCLE_BUBBLE = 0x141,
3616 #define SQ_DPP_ROW_HALF_MIRROR 0x141
|
| gfx_7_2_enum.h | 1464 SC_SC_PS_ENG_MULTICYCLE_BUBBLE = 0x141,
3576 #define SQ_V_MAD_F32 0x141
|
| /src/external/gpl3/binutils/dist/opcodes/ |
| sparc-opc.c | 2210 { "sha1", F3F(2, 0x36, 0x141), F3F(~2, ~0x36, ~0x141), "", F_FLOAT, HWCAP_SHA1, 0, v9e },
|
| /src/external/gpl3/binutils.old/dist/opcodes/ |
| sparc-opc.c | 2210 { "sha1", F3F(2, 0x36, 0x141), F3F(~2, ~0x36, ~0x141), "", F_FLOAT, HWCAP_SHA1, 0, v9e },
|
| /src/external/gpl3/gdb.old/dist/opcodes/ |
| sparc-opc.c | 2210 { "sha1", F3F(2, 0x36, 0x141), F3F(~2, ~0x36, ~0x141), "", F_FLOAT, HWCAP_SHA1, 0, v9e },
|
