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    Searched refs:x145 (Results 1 - 20 of 20) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
ppsmc.h 135 #define PPSMC_MSG_SCLKDPM_SetEnabledMask ((uint16_t) 0x145)
  /src/sys/external/bsd/drm2/dist/drm/radeon/
ppsmc.h 132 #define PPSMC_MSG_SCLKDPM_SetEnabledMask ((uint16_t) 0x145)
  /src/sys/external/bsd/drm2/dist/drm/amd/powerplay/inc/
fiji_ppsmc.h 247 #define PPSMC_MSG_SCLKDPM_SetEnabledMask ((uint16_t) 0x145)
smu7_ppsmc.h 244 #define PPSMC_MSG_SCLKDPM_SetEnabledMask ((uint16_t) 0x145)
tonga_ppsmc.h 271 #define PPSMC_MSG_SCLKDPM_SetEnabledMask ((uint16_t) 0x145)
  /src/sys/external/gpl2/dts/dist/include/dt-bindings/input/
linux-event-codes.h 408 #define BTN_TOOL_FINGER 0x145
  /src/sys/dev/ic/
rt2860reg.h 1034 #define RT5390_EEPROM_IQ_PHASE_CAL_TX0_CH36_TO_CH64_5GHZ 0x145
  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gmc/
gmc_7_1_d.h 1226 #define ixMC_IO_DEBUG_DQB2H_RX_VREF_CAL_D0 0x145
gmc_8_1_d.h 1330 #define ixMC_IO_DEBUG_DQB2H_RX_VREF_CAL_D0 0x145
  /src/sys/dev/microcode/aic7xxx/
aic79xx_reg.h 2112 ahd_print_register(NULL, 0, "SCSISEQ_TEMPLATE", 0x145, regvalue, cur_col, wrap)
3601 #define SCSISEQ_TEMPLATE 0x145
  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gca/
gfx_7_2_enum.h 1468 SC_PA3_SC_FPOV_WE = 0x145,
3580 #define SQ_V_CUBESC_F32 0x145
gfx_8_0_enum.h 453 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO2__1BLOCK_2TO2= 0x145,
1653 SC_PA3_SC_FPOV_WE = 0x145,
gfx_8_1_enum.h 453 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO2__1BLOCK_2TO2= 0x145,
1671 SC_PA3_SC_FPOV_WE = 0x145,
  /src/sys/lib/libkern/arch/hppa/
milli.S 1373 x145: sh3add %r26,%r26,%r1 ! sh3add %r1,0,%r1 ! b e_t0 ! sh1add %r1,%r26,%r1 label
  /src/sys/arch/sparc64/sparc64/
locore.s 827 STRAP(0x144); STRAP(0x145); STRAP(0x146); STRAP(0x147)
1034 STRAP(0x140); STRAP(0x141); STRAP(0x142); STRAP(0x143); STRAP(0x144); STRAP(0x145); STRAP(0x146); STRAP(0x147)
  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/dce/
dce_8_0_d.h 1044 #define mmDP_DTO1_PHASE 0x145
dce_10_0_d.h 1202 #define mmDP_DTO1_PHASE 0x145
dce_11_0_d.h 1014 #define mmDP_DTO1_PHASE 0x145
dce_11_2_d.h 1089 #define mmDP_DTO1_PHASE 0x145
  /src/sys/dev/pci/cxgb/
cxgb_regs.h 4751 #define A_TP_EGRESS_CONFIG 0x145

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