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  /src/sys/external/bsd/drm2/dist/drm/nouveau/nvkm/engine/gr/
nouveau_nvkm_engine_gr_ctxgp104.c 35 .bundle_min_gpm_fifo_depth = 0x180,
nouveau_nvkm_engine_gr_ctxgp107.c 43 .bundle_min_gpm_fifo_depth = 0x180,
nouveau_nvkm_engine_gr_ctxgk110b.c 91 .bundle_min_gpm_fifo_depth = 0x180,
nouveau_nvkm_engine_gr_ctxtu102.c 84 .bundle_min_gpm_fifo_depth = 0x180,
  /src/sys/arch/zaurus/dev/
wm8750reg.h 84 #define SRATE_BCM_MASK 0x180
85 #define SRATE_GET_BCM(x) (((x) >> 7) & 0x180)
130 #define ALC1_ALCSEL_MASK 0x180
131 #define ALC1_GET_ALCSEL(x) (((x) >> 7) & 0x180)
190 #define ADCTL2_OUTSW3_MASK 0x180
191 #define ADCTL2_GET_OUTSW3(x) (((x) >> 7) & 0x180)
202 #define PWRMGMT1_VMIDSEL_MASK 0x180
203 #define PWRMGMT1_GET_VMIDSEL(x) (((x) >> 7) & 0x180)
224 #define ADCTL3_ADCLRM_MASK 0x180
225 #define ADCTL3_GET_ADCLRM(x) (((x) >> 7) & 0x180)
    [all...]
  /src/sys/arch/amiga/dev/
efareg.h 60 #define FATA1_PION_OFF_SECTOR 0x180
  /src/sys/arch/rs6000/include/
iocc.h 53 #define IOCC_IEE (IOCC_BASE + 0x180) /* intr enable */
  /src/sys/external/gpl2/dts/dist/arch/arm/boot/dts/
imx53-ppd.dts 1054 MX53_PAD_DISP0_DAT0__USBOH3_USBH2_DATA_0 0x180
1055 MX53_PAD_DISP0_DAT1__USBOH3_USBH2_DATA_1 0x180
1056 MX53_PAD_DISP0_DAT2__USBOH3_USBH2_DATA_2 0x180
1057 MX53_PAD_DISP0_DAT3__USBOH3_USBH2_DATA_3 0x180
1058 MX53_PAD_DISP0_DAT4__USBOH3_USBH2_DATA_4 0x180
1059 MX53_PAD_DISP0_DAT5__USBOH3_USBH2_DATA_5 0x180
1060 MX53_PAD_DISP0_DAT6__USBOH3_USBH2_DATA_6 0x180
1061 MX53_PAD_DISP0_DAT7__USBOH3_USBH2_DATA_7 0x180
1062 MX53_PAD_DISP0_DAT10__USBOH3_USBH2_STP 0x180
1063 MX53_PAD_DISP0_DAT11__USBOH3_USBH2_NXT 0x180
    [all...]
imx53-cx9020.dts 235 MX53_PAD_FEC_REF_CLK__FEC_TX_CLK 0x180
236 MX53_PAD_FEC_RX_ER__FEC_RX_ER 0x180
237 MX53_PAD_FEC_CRS_DV__FEC_RX_DV 0x180
238 MX53_PAD_FEC_RXD1__FEC_RDATA_1 0x180
239 MX53_PAD_FEC_RXD0__FEC_RDATA_0 0x180
imx53-qsb-common.dtsi 236 MX53_PAD_FEC_REF_CLK__FEC_TX_CLK 0x180
237 MX53_PAD_FEC_RX_ER__FEC_RX_ER 0x180
238 MX53_PAD_FEC_CRS_DV__FEC_RX_DV 0x180
239 MX53_PAD_FEC_RXD1__FEC_RDATA_1 0x180
240 MX53_PAD_FEC_RXD0__FEC_RDATA_0 0x180
  /src/sys/external/gpl2/dts/dist/include/dt-bindings/clock/
dm816.h 28 #define DM816_TIMER5_CLKCTRL DM816_CLKCTRL_INDEX(0x180)
  /src/sys/arch/ia64/include/
setjmp.h 77 #define J_F30 0x180
  /src/sys/arch/arm/nvidia/
tegra_ahcisatareg.h 37 #define TEGRA_SATA_CONFIGURATION_REG 0x180
  /src/sys/arch/alpha/pci/
lcareg.h 111 #define LCA_IOC_W_T_BASE0 (LCA_IOC_BASE + 0x180) /* Translated Base */
  /src/sys/arch/arm/clps711x/
clps711xreg.h 78 #define PS711X_MEMCFG1 0x180 /* Memory Configuration Register 1 */
  /src/sys/arch/arm/sunxi/
sunxi_can.h 134 #define SUNXI_CAN_RBUF_RBACK0 0x180
  /src/sys/arch/hpcmips/vr/
vrpiureg.h 135 #define PIUB_REG_OFFSSET 0x180
icureg.h 252 #define VR4102_SYSINT2_REG_W 0x180 /* Level1 System intr reg 2 */
256 #define VR4181_SYSINT2_REG_W 0x180 /* Level1 System intr reg 2 */
  /src/sys/arch/sh3/include/
exception.h 64 #define EXPEVT_RES_INST 0x180 /* Illegal instruction */
  /src/sys/dev/pcmcia/
if_cnwreg.h 98 #define CNW_EREG_EC 0x180
  /src/sys/arch/hp300/dev/
mtreg.h 37 #define MT7980ID 0x180
  /src/sys/dev/gpib/
mtreg.h 38 #define MT7980ID 0x180
  /src/sys/arch/arm/ti/
omap2_gpmcreg.h 108 #define GPMC_CONFIG1_6 0x180
131 #define GPMC_CONFIG1_6 0x180
  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/smu/
smu_8_0_d.h 161 #define mmMP0PUB_IND_INDEX 0x180
162 #define mmMP_SMUIF0_MP0PUB_IND_INDEX 0x180
195 #define mmMP0PUB_IND_INDEX_0 0x180
444 #define mmPWRHW_SMC_IND_INDEX 0x180
445 #define mmPWRHW0_PWRHW_SMC_IND_INDEX 0x180
  /src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/mediatek/
mt8192.dtsi 455 <0 0x10217600 0 0x180>;
468 <0 0x10217780 0 0x180>;
481 <0 0x10217900 0 0x180>;
507 <0 0x10217180 0 0x180>;
520 <0 0x10217380 0 0x180>;

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