| /src/sys/arch/hpcmips/vr/ |
| vr4181ecureg.h | 39 #define ECU_INTMSK_REG_W 0x1a /* interrupt mask */
|
| vrkiureg.h | 56 #define KIURST 0x1a
|
| vr4181aiureg.h | 75 #define VR4181AIU_SEQ_REG_W 0x1a /* sequencer */
|
| vrc4172pcsreg.h | 46 #define VRC2_EXCS3SELH 0x1a
|
| vrgiureg.h | 62 #define GIUINTHTSEL_H_REG_W 0x1a
|
| /src/sys/arch/i386/stand/lib/ |
| biosgetsystime.S | 43 int $0x1a
|
| biosgetrtc.S | 41 int $0x1a
|
| /src/crypto/external/apache2/openssl/include/openssl/ |
| fipskey.h | 26 0xf4, 0x55, 0x66, 0x50, 0xac, 0x31, 0xd3, 0x54, 0x61, 0x61, 0x0b, 0xac, 0x4e, 0xd8, 0x1b, 0x1a, 0x18, 0x1b, 0x2d, 0x8a, 0x43, 0xea, 0x28, 0x54, 0xcb, 0xae, 0x22, 0xca, 0x74, 0x56, 0x08, 0x13
|
| /src/crypto/external/bsd/openssl/include/openssl/ |
| fipskey.h | 25 0xf4, 0x55, 0x66, 0x50, 0xac, 0x31, 0xd3, 0x54, 0x61, 0x61, 0x0b, 0xac, 0x4e, 0xd8, 0x1b, 0x1a, 0x18, 0x1b, 0x2d, 0x8a, 0x43, 0xea, 0x28, 0x54, 0xcb, 0xae, 0x22, 0xca, 0x74, 0x56, 0x08, 0x13
|
| /src/external/gpl3/gdb.old/dist/sim/lm32/ |
| lm32-sim.h | 44 #define LM32_CSR_WP2 0x1a
|
| /src/external/gpl3/gdb/dist/sim/lm32/ |
| lm32-sim.h | 44 #define LM32_CSR_WP2 0x1a
|
| /src/sys/external/gpl2/dts/dist/include/dt-bindings/dma/ |
| x1000-dma.h | 29 #define X1000_DMA_MSC0_TX 0x1a
|
| x1830-dma.h | 29 #define X1830_DMA_MSC0_TX 0x1a
|
| jz4775-dma.h | 31 #define JZ4775_DMA_MSC0_TX 0x1a
|
| /src/external/gpl3/gdb.old/dist/gdb/testsuite/gdb.arch/ |
| aarch64-fp.c | 22 0x18, 0x19, 0x1a, 0x1b, 0x1c, 0x1d, 0x1e, 0x1f};
|
| /src/external/gpl3/gdb/dist/gdb/testsuite/gdb.arch/ |
| aarch64-fp.c | 22 0x18, 0x19, 0x1a, 0x1b, 0x1c, 0x1d, 0x1e, 0x1f};
|
| /src/sys/external/bsd/drm2/dist/drm/radeon/ |
| rs780_dpm.h | 99 #define RS780_FVTHROTPWMRANGE0_GPIO_DFLT 0x1a
100 #define RS780_FVTHROTPWMRANGE1_GPIO_DFLT 0x1a
|
| /src/sys/external/isc/libsodium/dist/test/default/ |
| scalarmult7.c | 8 0x1a, 0xf4, 0xeb, 0xa4, 0xa9, 0x8e, 0xaa, 0x9b, 0x4e, 0xea
14 0x1a, 0xf4, 0xeb, 0xa4, 0xa9, 0x8e, 0xaa, 0x9b, 0x4e, 0x6a
|
| /src/external/bsd/ntp/dist/include/ |
| icom.h | 37 #define R71 0x1a
82 #define V_SETW 0x1a /* read/write channel/bank data */
|
| /src/include/ |
| nlist.h | 71 #define N_SETB 0x1a /* bss set element symbol */
|
| /src/sys/arch/mips/include/ |
| cache_r5900.h | 45 #define CACHEOP_R5900_HINV_D 0x1a /* HIT INVALIDATE */
|
| /src/sys/dev/i2c/ |
| am2315reg.h | 53 #define AM2315_REGISTER_RETENTION_1a 0x1a
|
| au8522mod_8vsb.h | 42 { 0x80d8, 0x1a },
|
| /src/sys/dev/mii/ |
| rgephyreg.h | 69 #define RGEPHY_MII_PHYSR 0x1a /* PHY Specific status register */
|
| /src/sys/external/bsd/drm2/dist/drm/nouveau/nvkm/subdev/fb/ |
| nouveau_nvkm_subdev_fb_ramnv1a.c | 54 if (fb->subdev.device->chipset == 0x1a) {
|
