| /src/sys/dev/ic/ |
| bt463reg.h | 82 #define BT463_NCMAP_ENTRIES 0x210 /* 528 CMAP entries */
|
| igpioreg.h | 202 { "INTC1071", 0, 0, 65, 0x200, 0x210 },
203 { "INTC1071", 1, 66, 111, 0x200, 0x210 },
204 { "INTC1071", 2, 112, 145, 0x200, 0x210 },
205 { "INTC1071", 3, 146, 183, 0x200, 0x210 },
206 { "INTC1071", 4, 184, 261, 0x200, 0x210 },
|
| bcmgenetreg.h | 52 #define GENET_INTRL2_CPU_SET_MASK 0x210
|
| /src/games/bcd/ |
| bcd.c | 98 0x404, 0x402, 0x401, 0x280, 0x240, 0x220, 0x210, 0x208,
102 0x402, 0x401, 0x280, 0x240, 0x220, 0x210, 0x208, 0x204,
114 0x402, 0x401, 0x280, 0x240, 0x220, 0x210, 0x208, 0x204,
118 0x402, 0x401, 0x280, 0x240, 0x220, 0x210, 0x208, 0x204,
|
| /src/sys/arch/hpcmips/dev/ |
| plumicureg.h | 104 #define PLUM_INT_PCCIEN_REG 0x210
|
| /src/sys/arch/x86/pci/ |
| lpssreg.h | 39 #define LPSS_ACTIVELTR 0x210
|
| /src/sys/external/gpl2/dts/dist/include/dt-bindings/clock/ |
| lpc18xx-ccu.h | 23 #define CLK_APB1_I2C0 0x210
|
| /src/sys/arch/arm/cortex/ |
| pl310_reg.h | 98 #define L2C_EV_CTR0 0x210
|
| /src/sys/arch/arm/marvell/ |
| kirkwoodreg.h | 173 #define KIRKWOOD_MLMB_MICHR 0x210 /*Main Intr Cause High reg*/
|
| mv78xx0reg.h | 172 #define MV78XX0_ICI_IRQIMLR 0x210 /* IRQ Interrupt Mask Low */
|
| dovereg.h | 150 #define DOVE_DB_SMICR 0x210 /* Second Main Intr Cause reg */
|
| /src/sys/arch/evbmips/malta/ |
| maltareg.h | 144 #define MALTA_JMPRS (MALTA_FPGA_BASE + 0x210)
|
| /src/sys/arch/hppa/include/ |
| som.h | 37 #define SOM_PA11 0x210
|
| /src/lib/libmenu/ |
| menu.h | 52 #define REQ_NEXT_MATCH (KEY_MAX + 0x210)
|
| /src/sys/arch/amiga/dev/ |
| wdc_buddha.c | 146 if (bus_space_map(wdr->cmd_iot, 0x210+ch*0x80, 8, 0,
|
| /src/sys/arch/mips/adm5120/include/ |
| adm5120reg.h | 294 #define ADM5120_MPMC_SWP(__i) (0x210 + 0x020 * (__i))
|
| /src/sys/arch/powerpc/include/mpc8xx/ |
| spr.h | 42 #define SPR_IBAT0U 0x210 /* .68 Instruction BAT Reg 0 Upper */
|
| /src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/broadcom/stingray/ |
| stingray-pinctrl.dtsi | 305 0x210 MODE_NITRO /* nuart_txd */
312 0x210 MODE_NAND /* uart0_out */
|
| /src/sys/arch/arm/ti/ |
| omap2_gpmcreg.h | 159 #define GPMC_ECC5_RESULT 0x210
|
| /src/sys/arch/sparc64/dev/ |
| ffbreg.h | 155 #define FFB_FBC_CONSTY 0x210
|
| /src/sys/dev/bi/ |
| if_nireg.h | 71 #define NI_PDR 0x210
|
| /src/sys/dev/pci/ |
| cs4281reg.h | 151 #define CS4281_FSIC0 0x210 /* FIFO Status and Interrupt Control Register 0 */
|
| /src/external/lgpl3/gmp/dist/mpn/cray/ieee/ |
| invert_limb.c | 73 0x210, 0x20f, 0x20e, 0x20d, 0x20c, 0x20b, 0x20a, 0x209,
|
| /src/sys/arch/arm/nvidia/ |
| tegra210_pinmux.c | 193 TEGRA_PIN("ap_ready_pv5", 0x210, "rsvd0", "rsvd1", "rsvd2", "rsvd3"),
|
| /src/sys/arch/macppc/dev/ |
| kauai.c | 58 #define DMA_CONFIG_REG 0x210 /* UDMA access timing */
|
