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  /src/sys/dev/pci/
pciide_sis_reg.h 111 {0x9f4, 0x64a, 0x474, 0x254, 0x234, 0x224, 0x214};
if_tireg.h 128 #define TI_SRAM_ADDR_B 0x254 /* Tigon 2 only */
  /src/sys/arch/sparc64/dev/
ffbreg.h 171 #define FFB_FBC_FBC 0x254 /* Frame Buffer Control */
  /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
ppsmc.h 196 #define PPSMC_MSG_LoadUcodes ((uint16_t) 0x254)
  /src/sys/external/bsd/drm2/dist/drm/amd/powerplay/inc/
cz_ppsmc.h 140 #define PPSMC_MSG_ExecuteJob ((uint16_t) 0x254)
fiji_ppsmc.h 362 #define PPSMC_MSG_LoadUcodes ((uint16_t) 0x254)
smu7_ppsmc.h 358 #define PPSMC_MSG_LoadUcodes ((uint16_t) 0x254)
tonga_ppsmc.h 391 #define PPSMC_MSG_LoadUcodes ((uint16_t) 0x254)
  /src/sys/arch/arm/nvidia/
tegra210_pinmux.c 210 TEGRA_PIN("pk0", 0x254, "iqc0", "i2s5b", "rsvd2", "rsvd3"),
tegra_hdmireg.h 290 #define HDMI_NV_PDISP_SOR_REFCLK_REG 0x254
  /src/sys/external/gpl2/dts/dist/arch/arm/boot/dts/nxp/imx/
imxrt1050-pinfunc.h 161 #define MXRT1050_IOMUXC_GPIO_EMC_20_SEMC_ADDR12 0x064 0x254 0x000 0x0 0x0
162 #define MXRT1050_IOMUXC_GPIO_EMC_20_FLEXPWM2_PWM3_B 0x064 0x254 0x484 0x1 0x1
163 #define MXRT1050_IOMUXC_GPIO_EMC_20_LPUART4_RXD 0x064 0x254 0x540 0x2 0x1
164 #define MXRT1050_IOMUXC_GPIO_EMC_20_ENET_RX_DATA00 0x064 0x254 0x434 0x3 0x0
165 #define MXRT1050_IOMUXC_GPIO_EMC_20_TMR2_TIMER0 0x064 0x254 0x570 0x4 0x0
166 #define MXRT1050_IOMUXC_GPIO_EMC_20_GPIO4_IO20 0x064 0x254 0x000 0x5 0x0
imx6dl-pinfunc.h 818 #define MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x254 0x63c 0x000 0x0 0x0
819 #define MX6QDL_PAD_KEY_COL4__IPU1_SISG4 0x254 0x63c 0x000 0x1 0x0
820 #define MX6QDL_PAD_KEY_COL4__USB_OTG_OC 0x254 0x63c 0x920 0x2 0x1
821 #define MX6QDL_PAD_KEY_COL4__KEY_COL4 0x254 0x63c 0x000 0x3 0x0
822 #define MX6QDL_PAD_KEY_COL4__UART5_RTS_B 0x254 0x63c 0x918 0x4 0x2
823 #define MX6QDL_PAD_KEY_COL4__UART5_CTS_B 0x254 0x63c 0x000 0x4 0x0
824 #define MX6QDL_PAD_KEY_COL4__GPIO4_IO14 0x254 0x63c 0x000 0x5 0x0
imx6q-pinfunc.h 734 #define MX6QDL_PAD_GPIO_19__KEY_COL5 0x254 0x624 0x8e8 0x0 0x1
735 #define MX6QDL_PAD_GPIO_19__ENET_1588_EVENT0_OUT 0x254 0x624 0x000 0x1 0x0
736 #define MX6QDL_PAD_GPIO_19__SPDIF_OUT 0x254 0x624 0x000 0x2 0x0
737 #define MX6QDL_PAD_GPIO_19__CCM_CLKO1 0x254 0x624 0x000 0x3 0x0
738 #define MX6QDL_PAD_GPIO_19__ECSPI1_RDY 0x254 0x624 0x000 0x4 0x0
739 #define MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x254 0x624 0x000 0x5 0x0
740 #define MX6QDL_PAD_GPIO_19__ENET_TX_ER 0x254 0x624 0x000 0x6 0x0
imx25-pinfunc.h 80 #define MX25_PAD_A25__A25 0x03c 0x254 0x000 0x00 0x000
81 #define MX25_PAD_A25__GPIO_2_11 0x03c 0x254 0x000 0x05 0x000
82 #define MX25_PAD_A25__FEC_CRS 0x03c 0x254 0x508 0x07 0x000
imx35-pinfunc.h 642 #define MX35_PAD_SD2_DATA1__ESDHC2_DAT1 0x254 0x6b8 0x000 0x0 0x0
643 #define MX35_PAD_SD2_DATA1__UART3_TXD_MUX 0x254 0x6b8 0x000 0x1 0x0
644 #define MX35_PAD_SD2_DATA1__ESDHC1_DAT7 0x254 0x6b8 0x810 0x2 0x0
645 #define MX35_PAD_SD2_DATA1__IPU_CSI_D_5 0x254 0x6b8 0x944 0x3 0x1
646 #define MX35_PAD_SD2_DATA1__USB_TOP_USBH2_DATA_0 0x254 0x6b8 0x9cc 0x4 0x0
647 #define MX35_PAD_SD2_DATA1__GPIO2_3 0x254 0x6b8 0x8cc 0x5 0x1
imx6sl-pinfunc.h 937 #define MX6SL_PAD_SD2_CLK__SD2_CLK 0x254 0x55c 0x000 0x0 0x0
938 #define MX6SL_PAD_SD2_CLK__AUD4_RXFS 0x254 0x55c 0x5f0 0x1 0x2
939 #define MX6SL_PAD_SD2_CLK__ECSPI3_SCLK 0x254 0x55c 0x6b0 0x2 0x2
940 #define MX6SL_PAD_SD2_CLK__CSI_DATA00 0x254 0x55c 0x630 0x3 0x2
941 #define MX6SL_PAD_SD2_CLK__GPIO5_IO05 0x254 0x55c 0x000 0x5 0x0
imxrt1170-pinfunc.h 209 #define IOMUXC_GPIO_EMC_B1_00_SEMC_DATA00 0x010 0x254 0x0 0x0 0x0
210 #define IOMUXC_GPIO_EMC_B1_00_FLEXPWM4_PWM0_A 0x010 0x254 0x0 0x1 0x0
211 #define IOMUXC_GPIO_EMC_B1_00_GPIO_MUX1_IO00 0x010 0x254 0x0 0x5 0x0
212 #define IOMUXC_GPIO_EMC_B1_00_FLEXIO1_D00 0x010 0x254 0x0 0x8 0x0
213 #define IOMUXC_GPIO_EMC_B1_00_GPIO7_IO00 0x010 0x254 0x0 0xA 0x0
imx50-pinfunc.h 791 #define MX50_PAD_EPDC_SDCE4__EPCD_SDCE_4 0x254 0x5f0 0x000 0x0 0x0
792 #define MX50_PAD_EPDC_SDCE4__GPIO4_29 0x254 0x5f0 0x000 0x1 0x0
793 #define MX50_PAD_EPDC_SDCE4__ELCDIF_DAT_1 0x254 0x5f0 0x700 0x3 0x1
imx53-pinfunc.h 815 #define MX53_PAD_FEC_CRS_DV__FEC_RX_DV 0x254 0x5d0 0x000 0x0 0x0
816 #define MX53_PAD_FEC_CRS_DV__GPIO1_25 0x254 0x5d0 0x000 0x1 0x0
817 #define MX53_PAD_FEC_CRS_DV__ESAI1_SCKT 0x254 0x5d0 0x7e0 0x2 0x0
  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/oss/
oss_2_0_d.h 172 #define ixCLIENT1_CD2 0x254
oss_3_0_d.h 241 #define ixCLIENT1_CD2 0x254
  /src/sys/arch/arm/broadcom/
bcm53xx_reg.h 482 #define PCIE_SYS_EQ_TAIL_0 0x254
  /src/sys/arch/arm/xscale/
pxa2x0reg.h 604 #define LCDC_FSADR5 0x254 /* DMA ch5 frame source address */
  /src/sys/external/bsd/drm2/dist/include/drm/
drm_dp_helper.h 712 #define DP_TEST_80BIT_CUSTOM_PATTERN_39_32 0x254
  /src/sys/external/bsd/drm2/dist/drm/radeon/
cikd.h 432 #define SMC_RESP_0 0x254

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