| /src/external/gpl3/gcc/dist/gcc/ |
| rtl-tests.cc | 251 rtx x255 = gen_int_mode (poly_int64 (1, 255), QImode); local
256 ASSERT_NE (x1, x255);
260 ASSERT_KNOWN_EQ (const_poly_int_value (x255), poly_int64 (1, -1));
264 ASSERT_KNOWN_EQ (rtx_to_poly_int64 (x255), poly_int64 (1, -1));
265 ASSERT_MAYBE_NE (rtx_to_poly_int64 (x255), poly_int64 (1, 255));
|
| /src/external/gpl3/gcc.old/dist/gcc/ |
| rtl-tests.cc | 250 rtx x255 = gen_int_mode (poly_int64 (1, 255), QImode); local
255 ASSERT_NE (x1, x255);
259 ASSERT_KNOWN_EQ (const_poly_int_value (x255), poly_int64 (1, -1));
263 ASSERT_KNOWN_EQ (rtx_to_poly_int64 (x255), poly_int64 (1, -1));
264 ASSERT_MAYBE_NE (rtx_to_poly_int64 (x255), poly_int64 (1, 255));
|
| /src/external/lgpl3/gmp/dist/mpn/cray/ieee/ |
| invert_limb.c | 65 0x25e, 0x25d, 0x25c, 0x25a, 0x259, 0x257, 0x256, 0x255,
|
| /src/sys/external/bsd/drm2/dist/drm/amd/powerplay/inc/ |
| fiji_ppsmc.h | 363 #define PPSMC_MSG_PowerStateNotify ((uint16_t) 0x255)
|
| smu7_ppsmc.h | 359 #define PPSMC_MSG_PowerStateNotify ((uint16_t) 0x255)
|
| tonga_ppsmc.h | 392 #define PPSMC_MSG_PowerStateNotify ((uint16_t) 0x255)
|
| /src/sys/external/bsd/drm2/dist/include/drm/ |
| drm_dp_helper.h | 713 #define DP_TEST_80BIT_CUSTOM_PATTERN_47_40 0x255
|
| /src/crypto/external/bsd/heimdal/dist/lib/hx509/ref/ |
| pkcs11.h | 651 #define CKM_SHA224 (0x255)
|
| /src/sys/external/bsd/drm2/dist/drm/amd/powerplay/smumgr/ |
| amdgpu_iceland_smumgr.c | 85 { 0x17C, 0x172, 0x180, 0x1BC, 0x1B3, 0x1BD, 0x206, 0x200, 0x203, 0x25D, 0x25A, 0x255, 0x2C3, 0x2C5, 0x2B4 }
|
| amdgpu_vegam_smumgr.c | 74 { 0x17C, 0x172, 0x180, 0x1BC, 0x1B3, 0x1BD, 0x206, 0x200, 0x203, 0x25D, 0x25A, 0x255, 0x2C3, 0x2C5, 0x2B4 } },
|
| amdgpu_ci_smumgr.c | 88 { 0x17C, 0x172, 0x180, 0x1BC, 0x1B3, 0x1BD, 0x206, 0x200, 0x203, 0x25D, 0x25A, 0x255, 0x2C3, 0x2C5, 0x2B4 }
|
| amdgpu_polaris10_smumgr.c | 70 { 0x17C, 0x172, 0x180, 0x1BC, 0x1B3, 0x1BD, 0x206, 0x200, 0x203, 0x25D, 0x25A, 0x255, 0x2C3, 0x2C5, 0x2B4 } },
|
| amdgpu_tonga_smumgr.c | 78 0x25D, 0x25A, 0x255, 0x2C3, 0x2C5, 0x2B4}
|
| /src/external/gpl3/binutils/dist/opcodes/ |
| i386-mnem.h | 83 #define MN_vinserti64x2 0x255
|
| /src/external/gpl3/binutils.old/dist/opcodes/ |
| i386-mnem.h | 83 #define MN_vinserti64x2 0x255
|
| /src/external/gpl3/gdb.old/dist/opcodes/ |
| i386-mnem.h | 89 #define MN_sha1rnds4 0x255
|
| /src/external/gpl3/gdb/dist/opcodes/ |
| i386-mnem.h | 83 #define MN_vinserti64x2 0x255
|
| /src/sys/lib/libkern/arch/hppa/ |
| milli.S | 1593 x255: zdep %r26,23,24,%r1 ! comb,<> %r25,0,l0 ! sub %r1,%r26,%r1 ! b,n ret_t0 label
|
| /src/external/gpl3/gcc/dist/libgcc/config/pa/ |
| milli64.S | 2098 LSYM(x255) t0__256a0 ! a1_ne_0_b_l0 ! t0__t0ma0 ! b_n_ret_t0
|
| /src/external/gpl3/gcc.old/dist/libgcc/config/pa/ |
| milli64.S | 2084 LSYM(x255) t0__256a0 ! a1_ne_0_b_l0 ! t0__t0ma0 ! b_n_ret_t0
|
| /src/sys/external/bsd/drm2/dist/drm/radeon/ |
| radeon_ci_dpm.c | 70 { 0x17C, 0x172, 0x180, 0x1BC, 0x1B3, 0x1BD, 0x206, 0x200, 0x203, 0x25D, 0x25A, 0x255, 0x2C3, 0x2C5, 0x2B4 }
|
| /src/external/gpl3/binutils/dist/include/opcode/ |
| riscv-opc.h | 4249 #define CSR_VSIREG4 0x255
|
| /src/external/gpl3/binutils.old/dist/include/opcode/ |
| riscv-opc.h | 4220 #define CSR_VSIREG4 0x255
|
| /src/external/gpl3/gdb.old/dist/include/opcode/ |
| riscv-opc.h | 4160 #define CSR_VSIREG4 0x255
|
| /src/external/gpl3/gdb/dist/include/opcode/ |
| riscv-opc.h | 4220 #define CSR_VSIREG4 0x255
|
