Searched refs:BRW_PIPE_CONTROL (Results 1 - 13 of 13) sorted by relevance
| /xsrc/external/mit/xf86-video-intel/dist/src/uxa/ |
| H A D | intel_batchbuffer.c | 158 OUT_BATCH(BRW_PIPE_CONTROL | (4 - 2));
164 OUT_BATCH(BRW_PIPE_CONTROL | (4 - 2));
171 OUT_BATCH(BRW_PIPE_CONTROL | (4 - 2));
210 OUT_BATCH(BRW_PIPE_CONTROL | (4 - 2));
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| H A D | i965_3d.c | 40 OUT_BATCH(BRW_PIPE_CONTROL | (4 - 2));
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| H A D | i965_reg.h | 77 #define BRW_PIPE_CONTROL BRW_3D(3, 2, 0) macro
325 /* for BRW_PIPE_CONTROL */
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| H A D | i965_video.c | 950 OUT_BATCH(BRW_PIPE_CONTROL | pipe_ctl | 2);
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| /xsrc/external/mit/xf86-video-intel-2014/dist/src/uxa/ |
| H A D | intel_batchbuffer.c | 158 OUT_BATCH(BRW_PIPE_CONTROL | (4 - 2));
164 OUT_BATCH(BRW_PIPE_CONTROL | (4 - 2));
171 OUT_BATCH(BRW_PIPE_CONTROL | (4 - 2));
210 OUT_BATCH(BRW_PIPE_CONTROL | (4 - 2));
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| H A D | i965_3d.c | 40 OUT_BATCH(BRW_PIPE_CONTROL | (4 - 2));
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| H A D | i965_reg.h | 77 #define BRW_PIPE_CONTROL BRW_3D(3, 2, 0) macro
325 /* for BRW_PIPE_CONTROL */
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| H A D | i965_video.c | 951 OUT_BATCH(BRW_PIPE_CONTROL | pipe_ctl | 2);
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| /xsrc/external/mit/xf86-video-intel/dist/xvmc/ |
| H A D | i965_reg.h | 50 #define BRW_PIPE_CONTROL BRW_3D(3, 2, 0) macro
298 /* for BRW_PIPE_CONTROL */
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| /xsrc/external/mit/xf86-video-intel-2014/dist/xvmc/ |
| H A D | i965_reg.h | 50 #define BRW_PIPE_CONTROL BRW_3D(3, 2, 0) macro
298 /* for BRW_PIPE_CONTROL */
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| /xsrc/external/mit/xf86-video-intel-old/dist/src/ |
| H A D | i965_video.c | 845 OUT_BATCH(BRW_PIPE_CONTROL | pipe_ctl | 2);
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| H A D | i810_reg.h | 2619 #define BRW_PIPE_CONTROL BRW_3D(3, 2, 0) macro
2648 /* for BRW_PIPE_CONTROL */
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| H A D | i965_render.c | 1219 OUT_BATCH(BRW_PIPE_CONTROL | pipe_ctrl | 2);
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