Searched refs:BRW_PIPE_CONTROL_WC_FLUSH (Results 1 - 9 of 9) sorted by relevance

/xsrc/external/mit/xf86-video-intel/dist/src/uxa/
H A Dintel_batchbuffer.c172 OUT_BATCH(BRW_PIPE_CONTROL_WC_FLUSH |
211 OUT_BATCH(BRW_PIPE_CONTROL_WC_FLUSH |
H A Di965_3d.c42 BRW_PIPE_CONTROL_WC_FLUSH |
H A Di965_reg.h332 #define BRW_PIPE_CONTROL_WC_FLUSH (1 << 12) macro
/xsrc/external/mit/xf86-video-intel-2014/dist/src/uxa/
H A Dintel_batchbuffer.c172 OUT_BATCH(BRW_PIPE_CONTROL_WC_FLUSH |
211 OUT_BATCH(BRW_PIPE_CONTROL_WC_FLUSH |
H A Di965_3d.c42 BRW_PIPE_CONTROL_WC_FLUSH |
H A Di965_reg.h332 #define BRW_PIPE_CONTROL_WC_FLUSH (1 << 12) macro
/xsrc/external/mit/xf86-video-intel/dist/xvmc/
H A Di965_reg.h305 #define BRW_PIPE_CONTROL_WC_FLUSH (1 << 12) macro
/xsrc/external/mit/xf86-video-intel-2014/dist/xvmc/
H A Di965_reg.h305 #define BRW_PIPE_CONTROL_WC_FLUSH (1 << 12) macro
/xsrc/external/mit/xf86-video-intel-old/dist/src/
H A Di810_reg.h2654 #define BRW_PIPE_CONTROL_WC_FLUSH (1 << 12) macro

Completed in 18 milliseconds