Searched refs:CIK_UCONFIG_REG_OFFSET (Results 1 - 15 of 15) sorted by relevance

/xsrc/external/mit/MesaLib/dist/src/amd/vulkan/
H A Dradv_cs.h134 assert(reg >= CIK_UCONFIG_REG_OFFSET && reg < CIK_UCONFIG_REG_END);
138 radeon_emit(cs, (reg - CIK_UCONFIG_REG_OFFSET) >> 2);
144 assert(reg >= CIK_UCONFIG_REG_OFFSET && reg < CIK_UCONFIG_REG_END);
148 radeon_emit(cs, (reg - CIK_UCONFIG_REG_OFFSET) >> 2);
162 assert(reg >= CIK_UCONFIG_REG_OFFSET && reg < CIK_UCONFIG_REG_END);
172 radeon_emit(cs, (reg - CIK_UCONFIG_REG_OFFSET) >> 2 | (idx << 28));
179 assert(reg < CIK_UCONFIG_REG_OFFSET);
/xsrc/external/mit/MesaLib.old/dist/src/amd/vulkan/
H A Dradv_cs.h101 assert(reg >= CIK_UCONFIG_REG_OFFSET && reg < CIK_UCONFIG_REG_END);
105 radeon_emit(cs, (reg - CIK_UCONFIG_REG_OFFSET) >> 2);
118 assert(reg >= CIK_UCONFIG_REG_OFFSET && reg < CIK_UCONFIG_REG_END);
121 radeon_emit(cs, (reg - CIK_UCONFIG_REG_OFFSET) >> 2 | (idx << 28));
/xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/r600/
H A Dr600_cs.h186 assert(reg >= CIK_UCONFIG_REG_OFFSET && reg < CIK_UCONFIG_REG_END);
189 radeon_emit(cs, (reg - CIK_UCONFIG_REG_OFFSET) >> 2);
202 assert(reg >= CIK_UCONFIG_REG_OFFSET && reg < CIK_UCONFIG_REG_END);
205 radeon_emit(cs, (reg - CIK_UCONFIG_REG_OFFSET) >> 2 | (idx << 28));
H A Dr600d_common.h33 #define CIK_UCONFIG_REG_OFFSET 0x00030000 macro
/xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/radeonsi/
H A Dsi_build_pm4.h90 assert(reg >= CIK_UCONFIG_REG_OFFSET && reg < CIK_UCONFIG_REG_END);
93 radeon_emit(cs, (reg - CIK_UCONFIG_REG_OFFSET) >> 2);
107 assert(reg >= CIK_UCONFIG_REG_OFFSET && reg < CIK_UCONFIG_REG_END);
115 radeon_emit(cs, (reg - CIK_UCONFIG_REG_OFFSET) >> 2 | (idx << 28));
H A Dsi_pm4.c66 } else if (reg >= CIK_UCONFIG_REG_OFFSET && reg < CIK_UCONFIG_REG_END) {
68 reg -= CIK_UCONFIG_REG_OFFSET;
/xsrc/external/mit/MesaLib/dist/src/gallium/drivers/r600/
H A Dr600_cs.h186 assert(reg >= CIK_UCONFIG_REG_OFFSET && reg < CIK_UCONFIG_REG_END);
189 radeon_emit(cs, (reg - CIK_UCONFIG_REG_OFFSET) >> 2);
202 assert(reg >= CIK_UCONFIG_REG_OFFSET && reg < CIK_UCONFIG_REG_END);
205 radeon_emit(cs, (reg - CIK_UCONFIG_REG_OFFSET) >> 2 | (idx << 28));
H A Dr600d_common.h33 #define CIK_UCONFIG_REG_OFFSET 0x00030000 macro
/xsrc/external/mit/MesaLib/dist/src/gallium/drivers/radeonsi/
H A Dsi_build_pm4.h127 assert((reg) >= CIK_UCONFIG_REG_OFFSET && (reg) < CIK_UCONFIG_REG_END); \
129 radeon_emit(((reg) - CIK_UCONFIG_REG_OFFSET) >> 2); \
144 assert((reg) >= CIK_UCONFIG_REG_OFFSET && (reg) < CIK_UCONFIG_REG_END); \
151 radeon_emit(((reg) - CIK_UCONFIG_REG_OFFSET) >> 2 | ((idx) << 28)); \
261 assert((reg) < CIK_UCONFIG_REG_OFFSET); \
H A Dsi_pm4.c69 } else if (reg >= CIK_UCONFIG_REG_OFFSET && reg < CIK_UCONFIG_REG_END) {
71 reg -= CIK_UCONFIG_REG_OFFSET;
H A Dsi_cp_reg_shadowing.c44 offset = CIK_UCONFIG_REG_OFFSET;
/xsrc/external/mit/MesaLib/dist/src/amd/common/
H A Dsid.h36 #define CIK_UCONFIG_REG_OFFSET 0x00030000 macro
44 #define SI_UCONFIG_REG_SPACE_SIZE (CIK_UCONFIG_REG_END - CIK_UCONFIG_REG_OFFSET)
H A Dac_debug.c289 ac_parse_set_reg_packet(f, count, CIK_UCONFIG_REG_OFFSET, ib);
/xsrc/external/mit/MesaLib.old/dist/src/amd/common/
H A Dac_debug.c257 ac_parse_set_reg_packet(f, count, CIK_UCONFIG_REG_OFFSET, ib);
H A Dsid.h34 #define CIK_UCONFIG_REG_OFFSET 0x00030000 macro

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