Searched refs:CR40 (Results 1 - 10 of 10) sorted by relevance

/xsrc/external/mit/xf86-video-siliconmotion/dist/src/
H A Dsmilynx_crtc.c418 reg->CR40 [0x0] = HTotal & 0xFF;
419 reg->CR40 [0x1] = HBlankStart & 0xFF;
420 reg->CR40 [0x2] = HBlankEnd & 0x1F;
421 reg->CR40 [0x3] = HSyncStart & 0xFF;
422 reg->CR40 [0x4] = (HBlankEnd & 0x20) >> 5 << 7 |
424 reg->CR40 [0x5] = VTotal & 0xFF;
425 reg->CR40 [0x6] = VBlankStart & 0xFF;
426 reg->CR40 [0x7] = VBlankEnd & 0xFF;
427 reg->CR40 [0x8] = VSyncStart & 0xFF;
428 reg->CR40 [
[all...]
H A Dsmi.h150 CARD8 CR40[14], CR40_2[14]; member in struct:__anon910553c20108
H A Dsmilynx_hw.c246 save->CR40[i] = VGAIN8_INDEX(pSmi, vgaCRIndex, vgaCRData, 0x40 + i);
267 save->CR40[i] = VGAIN8_INDEX(pSmi, vgaCRIndex, vgaCRData, 0x40 + i);
415 restore->CR40[i]);
437 restore->CR40[i]);
/xsrc/external/mit/xf86-video-xgi/dist/src/
H A Dvb_init.c1262 XGI_SetReg((XGIIOADDRESS) P3d4 , 0x82 , pVBInfo->CR40[ 11 ][ XGINew_RAMType ] ) ; /* CR82 */
1263 XGI_SetReg((XGIIOADDRESS) P3d4 , 0x85 , pVBInfo->CR40[ 12 ][ XGINew_RAMType ] ) ; /* CR85 */
1264 XGI_SetReg((XGIIOADDRESS) P3d4 , 0x86 , pVBInfo->CR40[ 13 ][ XGINew_RAMType ] ) ; /* CR86 */
1279 XGI_SetReg((XGIIOADDRESS) P3d4 , 0x82 , pVBInfo->CR40[ 11 ][ XGINew_RAMType ] ) ; /* CR82 */
1280 XGI_SetReg((XGIIOADDRESS) P3d4 , 0x85 , pVBInfo->CR40[ 12 ][ XGINew_RAMType ] ) ; /* CR85 */
1281 XGI_SetReg((XGIIOADDRESS) P3d4 , 0x86 , pVBInfo->CR40[ 13 ][ XGINew_RAMType ] ) ; /* CR86 */
1289 XGI_SetReg((XGIIOADDRESS) P3d4 , 0x86 , pVBInfo->CR40[ 13 ][ XGINew_RAMType ] ) ;
1295 XGI_SetReg((XGIIOADDRESS) P3d4 , 0x85 , pVBInfo->CR40[ 12 ][ XGINew_RAMType ] ) ; /* CR85 */
1296 XGI_SetReg((XGIIOADDRESS) P3d4 , 0x82 , pVBInfo->CR40[ 11 ][ XGINew_RAMType ] ) ; /* CR82 */
1331 XGI_SetReg((XGIIOADDRESS) P3d4 , 0x82 , pVBInfo->CR40[ 1
[all...]
H A Dvb_struct.h475 DRAM8Type CR40[CR40_SIZE]; member in struct:_VB_DEVICE_INFO
H A Dvb_setmode.c345 (void) memcpy(pVBInfo->CR40, XGI340_CR41, sizeof(XGI340_CR41));
440 /* pVBInfo->CR40 = XGI27_cr41 ; */
441 (void) memcpy(pVBInfo->CR40, XGI27_cr41, sizeof(XGI27_cr41));
/xsrc/external/mit/xf86-video-s3virge/dist/src/
H A Ds3v.h131 unsigned char CR40, CR41, CR42, CR43, CR45; member in struct:__anon92930e910108
221 unsigned char CR38,CR39,CR40; member in struct:tagS3VRec
H A Ds3v_driver.c1505 save->CR40 = VGAIN8(vgaCRReg);
1831 /* S3_ViRGE_MX_SERIES(ps3v->Chipset) || CR40 reserved on MX */
1840 VGAOUT8(vgaCRReg, restore->CR40);
2737 /* S3_ViRGE_MX_SERIES(ps3v->Chipset) || CR40 reserved on MX */
2745 new->CR40 = VGAIN8(vgaCRReg) & ~0x01;
/xsrc/external/mit/xf86-video-savage/dist/src/
H A Dsavage_driver.h239 unsigned char CR40, CR41, CR42, CR43, CR45; member in struct:__anone89ec5cb0308
H A Dsavage_driver.c2340 save->CR40 = VGAIN8(vgaCRReg);
2780 VGAOUT8(vgaCRReg, restore->CR40);
3853 new->CR40 = VGAIN8(vgaCRReg) & ~0x01;

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