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  /xsrc/external/mit/xf86-video-nv/dist/src/
nv_local.h 81 (pNv)->FIFO[0x0010] = (data) << 2; \
86 #define READ_GET(pNv) ((pNv)->FIFO[0x0011] >> 2)
riva_hw.c 755 LOAD_FIXED_STATE(Riva,FIFO);
802 * Reset FIFO free and empty counts.
965 * Fill in FIFO pointers.
967 chip->Rop = (RivaRop *)&(chip->FIFO[0x00000000/4]);
968 chip->Clip = (RivaClip *)&(chip->FIFO[0x00002000/4]);
969 chip->Patt = (RivaPattern *)&(chip->FIFO[0x00004000/4]);
970 chip->Pixmap = (RivaPixmap *)&(chip->FIFO[0x00006000/4]);
971 chip->Blt = (RivaScreenBlt *)&(chip->FIFO[0x00008000/4]);
972 chip->Bitmap = (RivaBitmap *)&(chip->FIFO[0x0000A000/4]);
973 chip->Line = (RivaLine *)&(chip->FIFO[0x0000C000/4])
    [all...]
nv_type.h 45 U032 fifo; member in struct:_riva_hw_state
122 volatile U032 *FIFO;
riva_hw.h 32 * FIFO registers. *
261 * Non-FIFO registers.
271 volatile U032 *FIFO;
292 * FIFO registers.
332 * FIFO Free Count. Should attempt to yield processor if RIVA is busy.
riva_setup.c 257 MAP(FIFO, regBase + 0x00800000, 0x00010000);
nv_setup.c 431 pNv->FIFO = pNv->REGS + (0x00800000/4);
  /xsrc/external/mit/xf86-video-nsc/dist/src/gfx/
release.txt 157 * Modified the modeset code to set higher FIFO priority levels for high bandwidth
198 * Added fix for SC1200 issue #1121 (VIP FIFO bus request threshold bit
  /xsrc/external/mit/xterm/dist/
configure 786 --disable-fifo-lines disable FIFO-storage for saved-lines
20821 echo "$as_me:20821: checking if you want saved-lines stored as a FIFO" >&5
20822 echo $ECHO_N "checking if you want saved-lines stored as a FIFO... $ECHO_C" >&6
20824 # Check whether --enable-fifo-lines or --disable-fifo-lines was given.

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