Searched refs:FS_U0 (Results 1 - 8 of 8) sorted by relevance

/xsrc/external/mit/xf86-video-intel-old/dist/src/
H A Di915_3d.h82 #define FS_U0 ((REG_TYPE_U << 8) | 0) macro
H A Di915_render.c481 out_reg = FS_U0;
/xsrc/external/mit/xf86-video-intel/dist/src/uxa/
H A Di915_3d.h286 #define FS_U0 ((REG_TYPE_U << REG_TYPE_SHIFT) | 0) macro
/xsrc/external/mit/xf86-video-intel-2014/dist/src/uxa/
H A Di915_3d.h286 #define FS_U0 ((REG_TYPE_U << REG_TYPE_SHIFT) | 0) macro
/xsrc/external/mit/xf86-video-intel/dist/src/sna/
H A Dgen3_render.c1469 gen3_2d_perspective(sna, in, FS_U0);
1470 in = FS_U0;
1487 gen3_2d_perspective(sna, in, FS_U0);
1488 in = FS_U0;
1498 gen3_fs_mad(FS_U0, MASK_X | MASK_Y,
1502 gen3_fs_dp2add(FS_U0, MASK_X,
1503 gen3_fs_operand(FS_U0, X, Y, ZERO, ZERO),
1504 gen3_fs_operand(FS_U0, X, Y, ZERO, ZERO),
1506 gen3_fs_rsq(out, MASK_X, gen3_fs_operand(FS_U0, X, X, X, X));
1508 gen3_fs_operand(FS_U0,
[all...]
H A Dgen3_render.h1133 #define FS_U0 ((REG_TYPE_U << REG_TYPE_SHIFT) | 0) macro
/xsrc/external/mit/xf86-video-intel-2014/dist/src/sna/
H A Dgen3_render.c1445 gen3_2d_perspective(sna, in, FS_U0);
1446 in = FS_U0;
1463 gen3_2d_perspective(sna, in, FS_U0);
1464 in = FS_U0;
1474 gen3_fs_mad(FS_U0, MASK_X | MASK_Y,
1478 gen3_fs_dp2add(FS_U0, MASK_X,
1479 gen3_fs_operand(FS_U0, X, Y, ZERO, ZERO),
1480 gen3_fs_operand(FS_U0, X, Y, ZERO, ZERO),
1482 gen3_fs_rsq(out, MASK_X, gen3_fs_operand(FS_U0, X, X, X, X));
1484 gen3_fs_operand(FS_U0,
[all...]
H A Dgen3_render.h1133 #define FS_U0 ((REG_TYPE_U << REG_TYPE_SHIFT) | 0) macro

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