Searched refs:I915_ENGINE_CLASS_RENDER (Results 1 - 22 of 22) sorted by relevance

/xsrc/external/mit/MesaLib.old/dist/src/intel/tools/
H A Daub_read.c140 enum drm_i915_gem_engine_class engine = I915_ENGINE_CLASS_RENDER;
155 engine = I915_ENGINE_CLASS_RENDER;
196 engine = I915_ENGINE_CLASS_RENDER;
239 engine = I915_ENGINE_CLASS_RENDER;
H A Daubinator_error_decode.c88 { I915_ENGINE_CLASS_RENDER, 0, "ACTHD_UDW" },
96 { I915_ENGINE_CLASS_RENDER, 0, "RCS_RING_BUFFER_CTL" },
103 { I915_ENGINE_CLASS_RENDER, 0, "RCS_FAULT_REG" },
111 [I915_ENGINE_CLASS_RENDER] = "rcs",
129 { "render", I915_ENGINE_CLASS_RENDER, 0 },
178 case I915_ENGINE_CLASS_RENDER:
H A Daub_write.c367 [I915_ENGINE_CLASS_RENDER] = {
369 .engine_class = I915_ENGINE_CLASS_RENDER,
400 case I915_ENGINE_CLASS_RENDER:
417 [I915_ENGINE_CLASS_RENDER] = gen8_render_context_init,
422 [I915_ENGINE_CLASS_RENDER] = gen10_render_context_init,
501 write_engine_execlist_setup(aub, I915_ENGINE_CLASS_RENDER);
505 register_write_out(aub, HWS_PGA_RCSUNIT, aub->engine_setup[I915_ENGINE_CLASS_RENDER].pphwsp_addr);
721 [I915_ENGINE_CLASS_RENDER] = AUB_TRACE_TYPE_RING_PRB0,
H A Derror2aub.c213 { "rcs", I915_ENGINE_CLASS_RENDER, true },
218 { "render command stream", I915_ENGINE_CLASS_RENDER, false },
H A Dintel_dump_gpu.c196 return I915_ENGINE_CLASS_RENDER;
H A Daubinator_viewer_decoder.cpp45 ctx->engine = I915_ENGINE_CLASS_RENDER;
/xsrc/external/mit/MesaLib/dist/src/intel/tools/
H A Daub_read.c138 enum drm_i915_gem_engine_class engine = I915_ENGINE_CLASS_RENDER;
153 engine = I915_ENGINE_CLASS_RENDER;
194 engine = I915_ENGINE_CLASS_RENDER;
237 engine = I915_ENGINE_CLASS_RENDER;
H A Daub_write.c358 [I915_ENGINE_CLASS_RENDER] = {
360 .engine_class = I915_ENGINE_CLASS_RENDER,
454 case I915_ENGINE_CLASS_RENDER:
471 [I915_ENGINE_CLASS_RENDER] = gfx8_render_context_init,
476 [I915_ENGINE_CLASS_RENDER] = gfx10_render_context_init,
507 case I915_ENGINE_CLASS_RENDER: reg = HWS_PGA_RCSUNIT; break;
782 [I915_ENGINE_CLASS_RENDER] = AUB_TRACE_TYPE_RING_PRB0,
H A Derror2aub.c200 { "rcs", I915_ENGINE_CLASS_RENDER, true },
205 { "render command stream", I915_ENGINE_CLASS_RENDER, false },
534 aub_write_exec(&aub, 0, batch_bo->addr, 0, I915_ENGINE_CLASS_RENDER);
H A Daubinator_error_decode.c84 { I915_ENGINE_CLASS_RENDER, 0, "ACTHD_UDW" },
92 { I915_ENGINE_CLASS_RENDER, 0, "RCS_RING_BUFFER_CTL" },
99 { I915_ENGINE_CLASS_RENDER, 0, "RCS_FAULT_REG" },
107 [I915_ENGINE_CLASS_RENDER] = "rcs",
125 { "render", I915_ENGINE_CLASS_RENDER, 0 },
174 case I915_ENGINE_CLASS_RENDER:
H A Dintel_dump_gpu.c195 return I915_ENGINE_CLASS_RENDER;
H A Daubinator_viewer_decoder.cpp46 ctx->engine = I915_ENGINE_CLASS_RENDER;
/xsrc/external/mit/MesaLib/dist/src/intel/vulkan/
H A Danv_gem.c425 [I915_ENGINE_CLASS_RENDER] = -1,
429 [I915_ENGINE_CLASS_RENDER] =
430 anv_gem_count_engines(info, I915_ENGINE_CLASS_RENDER),
H A Danv_device.c692 anv_gem_count_engines(pdevice->engine_info, I915_ENGINE_CLASS_RENDER);
704 .engine_class = I915_ENGINE_CLASS_RENDER,
712 .engine_class = I915_ENGINE_CLASS_RENDER,
720 .engine_class = I915_ENGINE_CLASS_RENDER,
734 .engine_class = I915_ENGINE_CLASS_RENDER,
H A DgenX_state.c341 case I915_ENGINE_CLASS_RENDER:
/xsrc/external/mit/MesaLib.old/dist/src/intel/common/
H A Dgen_decoder.c168 group->engine_mask = I915_ENGINE_CLASS_TO_MASK(I915_ENGINE_CLASS_RENDER) |
188 group->engine_mask |= I915_ENGINE_CLASS_TO_MASK(I915_ENGINE_CLASS_RENDER);
H A Dgen_batch_decoder.c50 ctx->engine = I915_ENGINE_CLASS_RENDER;
/xsrc/external/mit/MesaLib/dist/src/intel/common/
H A Dintel_decoder.c168 group->engine_mask = I915_ENGINE_CLASS_TO_MASK(I915_ENGINE_CLASS_RENDER) |
188 group->engine_mask |= I915_ENGINE_CLASS_TO_MASK(I915_ENGINE_CLASS_RENDER);
H A Dintel_batch_decoder.c52 ctx->engine = I915_ENGINE_CLASS_RENDER;
/xsrc/external/mit/libdrm/dist/include/drm/
H A Di915_drm.h168 * @I915_ENGINE_CLASS_RENDER:
176 I915_ENGINE_CLASS_RENDER = 0, enumerator in enum:drm_i915_gem_engine_class
1558 * engine class (offset by 1, I915_ENGINE_CLASS_RENDER is reported as
1567 * I915_ENGINE_CLASS_RENDER, I915_ENGINE_CLASS_COPY, etc.
2432 * .engines = { { I915_ENGINE_CLASS_RENDER, 0 },
/xsrc/external/mit/MesaLib.old/dist/include/drm-uapi/
H A Di915_drm.h97 I915_ENGINE_CLASS_RENDER = 0, enumerator in enum:drm_i915_gem_engine_class
/xsrc/external/mit/MesaLib/dist/include/drm-uapi/
H A Di915_drm.h165 I915_ENGINE_CLASS_RENDER = 0, enumerator in enum:drm_i915_gem_engine_class
1423 * engine class (offset by 1, I915_ENGINE_CLASS_RENDER is reported as
1432 * I915_ENGINE_CLASS_RENDER, I915_ENGINE_CLASS_COPY, etc.
2072 * .engines = { { I915_ENGINE_CLASS_RENDER, 0 },

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