Searched refs:I915_TILING_Y (Results 1 - 25 of 88) sorted by relevance

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/xsrc/external/mit/MesaLib.old/dist/src/intel/isl/
H A Disl_drm.c44 return I915_TILING_Y;
67 case I915_TILING_Y:
/xsrc/external/mit/MesaLib/dist/src/intel/isl/
H A Disl_drm.c47 return I915_TILING_Y;
71 case I915_TILING_Y:
/xsrc/external/mit/xf86-video-intel/dist/src/sna/
H A Dgen6_common.h52 if (bo && bo->tiling == I915_TILING_Y)
103 if (src->tiling == I915_TILING_Y)
124 if (bo->tiling == I915_TILING_Y)
/xsrc/external/mit/MesaLib.old/dist/src/mesa/drivers/dri/i915/
H A Dintel_clear.c134 if (stencilRegion->tiling == I915_TILING_Y ||
154 if (irb->tiling == I915_TILING_Y || tri_mask & BUFFER_BIT_STENCIL)
H A Dintel_blit.c97 bool dst_y_tiled = dst_tiling == I915_TILING_Y;
98 bool src_y_tiled = src_tiling == I915_TILING_Y;
422 assert(region->tiling != I915_TILING_Y);
515 if (dst_tiling == I915_TILING_Y)
H A Dintel_tex_subimage.c64 if (intelImage->mt->region->tiling == I915_TILING_Y)
H A Dintel_regions.c302 case I915_TILING_Y:
331 case I915_TILING_Y:
H A Di830_texstate.c169 if (intelObj->mt->region->tiling == I915_TILING_Y)
H A Di915_texstate.c184 if (intelObj->mt->region->tiling == I915_TILING_Y)
H A Dintel_mipmap_tree.c135 return I915_TILING_Y;
188 bool y_or_x = tiling == (I915_TILING_Y | I915_TILING_X);
191 y_or_x ? I915_TILING_Y : tiling,
/xsrc/external/mit/MesaLib/dist/src/mesa/drivers/dri/i915/
H A Dintel_clear.c133 if (stencilRegion->tiling == I915_TILING_Y ||
153 if (irb->tiling == I915_TILING_Y || tri_mask & BUFFER_BIT_STENCIL)
H A Dintel_blit.c97 bool dst_y_tiled = dst_tiling == I915_TILING_Y;
98 bool src_y_tiled = src_tiling == I915_TILING_Y;
422 assert(region->tiling != I915_TILING_Y);
515 if (dst_tiling == I915_TILING_Y)
H A Dintel_tex_subimage.c64 if (intelImage->mt->region->tiling == I915_TILING_Y)
H A Dintel_regions.c250 case I915_TILING_Y:
279 case I915_TILING_Y:
H A Di830_texstate.c169 if (intelObj->mt->region->tiling == I915_TILING_Y)
H A Di915_texstate.c184 if (intelObj->mt->region->tiling == I915_TILING_Y)
H A Dintel_mipmap_tree.c135 return I915_TILING_Y;
188 bool y_or_x = tiling == (I915_TILING_Y | I915_TILING_X);
191 y_or_x ? I915_TILING_Y : tiling,
/xsrc/external/mit/xf86-video-intel/dist/src/uxa/
H A Dintel_batchbuffer.h218 ((intel->BR_tiling[0] == I915_TILING_Y) ? BCS_SWCTRL_DST_Y : 0) | \
219 ((intel->BR_tiling[1] == I915_TILING_Y) ? BCS_SWCTRL_SRC_Y : 0)); \
H A Dintel_memory.c125 unsigned long tile_width = (tiling_mode == I915_TILING_Y) ? 128 : 512;
H A Di830_render.c300 == I915_TILING_Y)
592 == I915_TILING_Y)
H A Dintel_present.c273 if (tiling == I915_TILING_Y)
H A Dintel_uxa.c190 if (priv->tiling == I915_TILING_Y && INTEL_INFO(intel)->gen < 060)
579 tile_width = (tiling == I915_TILING_Y) ? 128 : 512;
1014 tiling = I915_TILING_Y;
1029 if (h <= 16 && tiling == I915_TILING_Y)
/xsrc/external/mit/xf86-video-intel-2014/dist/src/uxa/
H A Dintel_memory.c125 unsigned long tile_width = (tiling_mode == I915_TILING_Y) ? 128 : 512;
H A Di830_render.c300 == I915_TILING_Y)
592 == I915_TILING_Y)
H A Dintel_uxa.c554 tile_width = (tiling == I915_TILING_Y) ? 128 : 512;
989 tiling = I915_TILING_Y;
1004 if (h <= 16 && tiling == I915_TILING_Y)

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