Searched refs:IR3_REG_CONST (Results 1 - 19 of 19) sorted by relevance

/xsrc/external/mit/MesaLib.old/dist/src/freedreno/ir3/
H A Dir3_cp.c81 flags &= (IR3_REG_CONST | IR3_REG_IMMED |
118 valid_flags = IR3_REG_IMMED | IR3_REG_CONST | IR3_REG_RELATIV;
124 IR3_REG_CONST | IR3_REG_RELATIV;
132 if (flags & (IR3_REG_CONST | IR3_REG_IMMED)) {
139 if ((flags & IR3_REG_CONST) && (reg->flags & IR3_REG_CONST))
152 IR3_REG_CONST | IR3_REG_RELATIV;
157 if (flags & (IR3_REG_CONST | IR3_REG_RELATIV)) {
163 if (flags & IR3_REG_CONST) {
173 if (flags & (IR3_REG_CONST | IR3_REG_IMME
[all...]
H A Dir3.c115 if (reg->flags & IR3_REG_CONST) {
177 IR3_REG_R | IR3_REG_CONST | IR3_REG_HALF | IR3_REG_RELATIV);
179 cat1->src_rel_c = !!(src->flags & IR3_REG_CONST);
182 IR3_REG_R | IR3_REG_CONST | IR3_REG_HALF);
183 cat1->src_c = !!(src->flags & IR3_REG_CONST);
231 IR3_REG_RELATIV | IR3_REG_CONST | IR3_REG_R |
233 cat2->rel1.src1_c = !!(src1->flags & IR3_REG_CONST);
235 } else if (src1->flags & IR3_REG_CONST) {
238 IR3_REG_CONST | IR3_REG_R | IR3_REG_HALF);
257 IR3_REG_RELATIV | IR3_REG_CONST | IR3_REG_
[all...]
H A Dir3_print.c124 if (reg->flags & IR3_REG_CONST)
133 if (reg->flags & IR3_REG_CONST)
H A Dir3.h63 IR3_REG_CONST = 0x001, enumerator in enum:ir3_register::__anond9a07c730103
793 if (r->flags & (IR3_REG_CONST | IR3_REG_IMMED))
1068 ir3_reg_create(mov, n, IR3_REG_CONST);
1083 ir3_reg_create(mov, 0, IR3_REG_CONST | IR3_REG_RELATIV)->array.offset = n;
H A Dir3_ra.c394 if (reg->flags & (IR3_REG_CONST | IR3_REG_IMMED))
/xsrc/external/mit/MesaLib/dist/src/freedreno/isa/
H A Dencode.c104 if (src->flags & IR3_REG_CONST) {
109 } else if (src->flags & IR3_REG_CONST) {
264 if (reg->flags & IR3_REG_CONST) {
269 } else if (reg->flags & IR3_REG_CONST) {
287 if (reg->flags & IR3_REG_CONST) {
292 } else if (reg->flags & (IR3_REG_CONST | IR3_REG_IMMED)) {
/xsrc/external/mit/MesaLib/dist/src/freedreno/ir3/
H A Dir3_cse.c46 if (src->flags & IR3_REG_CONST)
78 if (i1_reg->flags & IR3_REG_CONST) {
H A Dir3.c97 if (reg->flags & IR3_REG_CONST) {
779 flags &= (IR3_REG_CONST | IR3_REG_IMMED | IR3_REG_FNEG | IR3_REG_FABS |
827 if (flags & ~(IR3_REG_IMMED | IR3_REG_CONST | IR3_REG_SHARED))
849 IR3_REG_IMMED | IR3_REG_CONST | IR3_REG_RELATIV | IR3_REG_SHARED;
855 valid_flags = ir3_cat2_absneg(instr->opc) | IR3_REG_CONST |
861 if (flags & (IR3_REG_CONST | IR3_REG_IMMED | IR3_REG_SHARED)) {
868 if ((flags & (IR3_REG_CONST | IR3_REG_SHARED)) &&
869 (reg->flags & (IR3_REG_CONST | IR3_REG_SHARED)))
884 valid_flags |= IR3_REG_CONST;
886 valid_flags |= IR3_REG_CONST;
[all...]
H A Dir3_lower_parallelcopy.c58 } else if (reg->flags & IR3_REG_CONST) {
60 .flags = IR3_REG_CONST,
265 else if (entry->src.flags & IR3_REG_CONST)
299 assert(!(entry->src.flags & (IR3_REG_IMMED | IR3_REG_CONST)));
379 !(entry->src.flags & (IR3_REG_IMMED | IR3_REG_CONST))) {
H A Dir3_cp.c139 *dstflags |= srcflags & IR3_REG_CONST;
167 new_flags |= IR3_REG_CONST;
289 new_flags |= IR3_REG_CONST;
403 if (src_reg->flags & IR3_REG_CONST) {
H A Dir3_print.c277 if (reg->flags & IR3_REG_CONST)
284 if (reg->flags & IR3_REG_CONST)
H A Dir3_delay.c333 if (src->flags & (IR3_REG_IMMED | IR3_REG_CONST))
H A Dir3_postsched.c454 if (reg->flags & (IR3_REG_CONST | IR3_REG_IMMED))
715 (IR3_REG_CONST | IR3_REG_IMMED | IR3_REG_RELATIV | IR3_REG_FNEG |
H A Dir3.h102 IR3_REG_CONST = 0x001, enumerator in enum:ir3_register::__anon3fdcb7e60103
852 if (!(instr->srcs[0]->flags & IR3_REG_CONST))
1180 if (r->flags & (IR3_REG_CONST | IR3_REG_IMMED))
1754 ir3_src_create(mov, n, IR3_REG_CONST | flags);
1775 ir3_src_create(mov, 0, IR3_REG_CONST | IR3_REG_RELATIV)->array.offset = n;
H A Dir3_spill.c628 } else if (val->flags & IR3_REG_CONST) {
629 src->flags = IR3_REG_CONST | (val->flags & IR3_REG_HALF);
664 if (val->flags & (IR3_REG_CONST | IR3_REG_IMMED)) {
678 IR3_REG_CONST | IR3_REG_SSA |
1177 assert(src->flags & (IR3_REG_CONST | IR3_REG_IMMED));
1178 if (src->flags & IR3_REG_CONST) {
1452 if ((pred_val->flags & (IR3_REG_IMMED | IR3_REG_CONST)) ||
H A Dir3_parser.y1172 const: T_CONSTANT { $$ = new_src($1, IR3_REG_CONST); }
1226 relative_const: 'c' '<' T_A0 offset '>' { new_src(0, IR3_REG_RELATIV | IR3_REG_CONST)->array.offset = $4; }
1227 | T_HC '<' T_A0 offset '>' { new_src(0, IR3_REG_RELATIV | IR3_REG_CONST | IR3_REG_HALF)->array.offset = $4; }
H A Dir3_ra_validate.c295 if (src->flags & (IR3_REG_IMMED | IR3_REG_CONST)) {
H A Dir3_sched.c244 if (src->flags & (IR3_REG_IMMED | IR3_REG_CONST))
/xsrc/external/mit/MesaLib/dist/src/freedreno/ir3/tests/
H A Ddelay.c132 if (reg->flags & (IR3_REG_CONST | IR3_REG_IMMED))

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