Searched refs:MI_BATCH_BUFFER_START (Results 1 - 13 of 13) sorted by relevance

/xsrc/external/mit/xf86-video-intel-old/dist/src/
H A Di830_batchbuffer.c49 OUT_RING(MI_BATCH_BUFFER_START | (2 << 6));
H A Dbrw_defines.h50 #define MI_BATCH_BUFFER_START 0x31
H A Di810_reg.h2567 #define MI_BATCH_BUFFER_START (0x31 << 23) macro
/xsrc/external/mit/xf86-video-intel/dist/src/uxa/
H A Dbrw_defines.h50 #define MI_BATCH_BUFFER_START 0x31
/xsrc/external/mit/xf86-video-intel/dist/xvmc/
H A Dbrw_defines.h50 #define MI_BATCH_BUFFER_START 0x31
/xsrc/external/mit/xf86-video-intel-2014/dist/src/uxa/
H A Dbrw_defines.h50 #define MI_BATCH_BUFFER_START 0x31
/xsrc/external/mit/xf86-video-intel-2014/dist/xvmc/
H A Dbrw_defines.h50 #define MI_BATCH_BUFFER_START 0x31
/xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/i915/
H A Di915_reg.h922 #define MI_BATCH_BUFFER_START (0x31<<23) macro
/xsrc/external/mit/MesaLib/dist/src/gallium/drivers/i915/
H A Di915_reg.h890 #define MI_BATCH_BUFFER_START (0x31 << 23) macro
/xsrc/external/mit/MesaLib/dist/src/intel/common/
H A Dmi_builder.h1309 mi_builder_emit(b, GENX(MI_BATCH_BUFFER_START), bbs) {
1346 struct GENX(MI_BATCH_BUFFER_START) bbs = { GENX(MI_BATCH_BUFFER_START_header) };
/xsrc/external/mit/xf86-video-intel/dist/src/legacy/i810/
H A Di810_reg.h2559 #define MI_BATCH_BUFFER_START (0x31 << 23) macro
/xsrc/external/mit/xf86-video-intel-2014/dist/src/legacy/i810/
H A Di810_reg.h2559 #define MI_BATCH_BUFFER_START (0x31 << 23) macro
/xsrc/external/mit/MesaLib/dist/docs/relnotes/
H A D21.1.0.rst2712 - intel/batch_decoder: Don't follow predicated MI_BATCH_BUFFER_START

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