Searched refs:PIPE_CONTROL_CACHE_FLUSH_BITS (Results 1 - 12 of 12) sorted by relevance

/xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/iris/
H A Diris_pipe_control.c60 if ((flags & PIPE_CONTROL_CACHE_FLUSH_BITS) &&
73 iris_emit_end_of_pipe_sync(batch, flags & PIPE_CONTROL_CACHE_FLUSH_BITS);
74 flags &= ~(PIPE_CONTROL_CACHE_FLUSH_BITS | PIPE_CONTROL_CS_STALL);
H A Diris_context.h219 #define PIPE_CONTROL_CACHE_FLUSH_BITS \ macro
/xsrc/external/mit/MesaLib/dist/src/gallium/drivers/iris/
H A Diris_pipe_control.c62 if ((flags & PIPE_CONTROL_CACHE_FLUSH_BITS) &&
76 flags & PIPE_CONTROL_CACHE_FLUSH_BITS);
77 flags &= ~(PIPE_CONTROL_CACHE_FLUSH_BITS | PIPE_CONTROL_CS_STALL);
187 const uint32_t all_flush_bits = (PIPE_CONTROL_CACHE_FLUSH_BITS |
274 if (bits & PIPE_CONTROL_CACHE_FLUSH_BITS)
H A Diris_context.h343 #define PIPE_CONTROL_CACHE_FLUSH_BITS \ macro
H A Diris_state.c7401 if ((flags & (PIPE_CONTROL_CACHE_FLUSH_BITS |
/xsrc/external/mit/MesaLib.old/dist/src/mesa/drivers/dri/i965/
H A Dgen8_multisample_state.c67 PIPE_CONTROL_CACHE_FLUSH_BITS |
H A Dbrw_pipe_control.c42 (flags & PIPE_CONTROL_CACHE_FLUSH_BITS) &&
55 brw_emit_end_of_pipe_sync(brw, (flags & PIPE_CONTROL_CACHE_FLUSH_BITS));
56 flags &= ~(PIPE_CONTROL_CACHE_FLUSH_BITS | PIPE_CONTROL_CS_STALL);
H A Dbrw_pipe_control.h68 #define PIPE_CONTROL_CACHE_FLUSH_BITS \ macro
/xsrc/external/mit/MesaLib/dist/src/gallium/drivers/crocus/
H A Dcrocus_pipe_control.c65 (flags & PIPE_CONTROL_CACHE_FLUSH_BITS) &&
79 flags & PIPE_CONTROL_CACHE_FLUSH_BITS);
80 flags &= ~(PIPE_CONTROL_CACHE_FLUSH_BITS | PIPE_CONTROL_CS_STALL);
H A Dcrocus_context.h262 #define PIPE_CONTROL_CACHE_FLUSH_BITS \ macro
/xsrc/external/mit/MesaLib/dist/src/mesa/drivers/dri/i965/
H A Dbrw_pipe_control.c42 (flags & PIPE_CONTROL_CACHE_FLUSH_BITS) &&
55 brw_emit_end_of_pipe_sync(brw, (flags & PIPE_CONTROL_CACHE_FLUSH_BITS));
56 flags &= ~(PIPE_CONTROL_CACHE_FLUSH_BITS | PIPE_CONTROL_CS_STALL);
H A Dbrw_pipe_control.h68 #define PIPE_CONTROL_CACHE_FLUSH_BITS \ macro

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