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    Searched refs:PIPE_CONTROL_DATA_CACHE_FLUSH (Results 1 - 25 of 27) sorted by relevancy

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  /xsrc/external/mit/MesaLib/dist/src/mesa/drivers/dri/i965/
brw_pipe_control.h 60 PIPE_CONTROL_DATA_CACHE_FLUSH = (1 << 19),
69 (PIPE_CONTROL_DEPTH_CACHE_FLUSH | PIPE_CONTROL_DATA_CACHE_FLUSH | \
genX_pipe_control.c 365 PIPE_CONTROL_DATA_CACHE_FLUSH)))) {
458 PIPE_CONTROL_DATA_CACHE_FLUSH;
472 pc.DCFlushEnable = flags & PIPE_CONTROL_DATA_CACHE_FLUSH;
gfx7_l3_state.c 88 PIPE_CONTROL_DATA_CACHE_FLUSH |
115 PIPE_CONTROL_DATA_CACHE_FLUSH |
brw_pipe_control.c 365 PIPE_CONTROL_DATA_CACHE_FLUSH |
brw_misc_state.c 528 devinfo->ver >= 7 ? PIPE_CONTROL_DATA_CACHE_FLUSH : 0;
758 devinfo->ver >= 7 ? PIPE_CONTROL_DATA_CACHE_FLUSH : 0;
brw_program.c 352 unsigned bits = PIPE_CONTROL_DATA_CACHE_FLUSH | PIPE_CONTROL_CS_STALL;
  /xsrc/external/mit/MesaLib.old/dist/src/mesa/drivers/dri/i965/
brw_pipe_control.h 60 PIPE_CONTROL_DATA_CACHE_FLUSH = (1 << 19),
69 (PIPE_CONTROL_DEPTH_CACHE_FLUSH | PIPE_CONTROL_DATA_CACHE_FLUSH | \
genX_pipe_control.c 361 PIPE_CONTROL_DATA_CACHE_FLUSH)))) {
454 PIPE_CONTROL_DATA_CACHE_FLUSH;
468 pc.DCFlushEnable = flags & PIPE_CONTROL_DATA_CACHE_FLUSH;
gen7_l3_state.c 88 PIPE_CONTROL_DATA_CACHE_FLUSH |
115 PIPE_CONTROL_DATA_CACHE_FLUSH |
brw_pipe_control.c 361 PIPE_CONTROL_DATA_CACHE_FLUSH |
brw_misc_state.c 529 devinfo->gen >= 7 ? PIPE_CONTROL_DATA_CACHE_FLUSH : 0;
669 devinfo->gen >= 7 ? PIPE_CONTROL_DATA_CACHE_FLUSH : 0;
brw_program.c 313 unsigned bits = PIPE_CONTROL_DATA_CACHE_FLUSH | PIPE_CONTROL_CS_STALL;
  /xsrc/external/mit/MesaLib/dist/src/gallium/drivers/iris/
iris_pipe_control.c 193 [IRIS_DOMAIN_DATA_WRITE] = PIPE_CONTROL_DATA_CACHE_FLUSH,
201 [IRIS_DOMAIN_DATA_WRITE] = PIPE_CONTROL_DATA_CACHE_FLUSH,
296 PIPE_CONTROL_DATA_CACHE_FLUSH |
341 unsigned bits = PIPE_CONTROL_DATA_CACHE_FLUSH | PIPE_CONTROL_CS_STALL;
iris_fine_fence.c 71 PIPE_CONTROL_DATA_CACHE_FLUSH;
iris_context.h 333 PIPE_CONTROL_DATA_CACHE_FLUSH = (1 << 19),
345 PIPE_CONTROL_DATA_CACHE_FLUSH | \
iris_state.c 412 PIPE_CONTROL_DATA_CACHE_FLUSH |
658 PIPE_CONTROL_DATA_CACHE_FLUSH |
7395 if ((flags & PIPE_CONTROL_DATA_CACHE_FLUSH))
7414 if ((flags & PIPE_CONTROL_DATA_CACHE_FLUSH))
7727 PIPE_CONTROL_DATA_CACHE_FLUSH)))) {
7794 PIPE_CONTROL_DATA_CACHE_FLUSH;
7820 (flags & PIPE_CONTROL_DATA_CACHE_FLUSH) ? "DC " : "",
7852 pc.DCFlushEnable = flags & PIPE_CONTROL_DATA_CACHE_FLUSH;
iris_resource.c 2545 PIPE_CONTROL_DATA_CACHE_FLUSH;
2555 flush |= PIPE_CONTROL_DATA_CACHE_FLUSH;
  /xsrc/external/mit/MesaLib/dist/src/gallium/drivers/crocus/
crocus_pipe_control.c 218 PIPE_CONTROL_DATA_CACHE_FLUSH |
285 PIPE_CONTROL_DATA_CACHE_FLUSH |
335 unsigned bits = PIPE_CONTROL_DATA_CACHE_FLUSH | PIPE_CONTROL_CS_STALL;
crocus_fine_fence.c 77 PIPE_CONTROL_DATA_CACHE_FLUSH;
crocus_context.h 253 PIPE_CONTROL_DATA_CACHE_FLUSH = (1 << 19),
264 PIPE_CONTROL_DATA_CACHE_FLUSH | \
crocus_monitor.c 125 PIPE_CONTROL_DATA_CACHE_FLUSH |
crocus_state.c 429 batch->screen->devinfo.ver >= 7 ? PIPE_CONTROL_DATA_CACHE_FLUSH : 0;
1082 PIPE_CONTROL_DATA_CACHE_FLUSH |
1109 PIPE_CONTROL_DATA_CACHE_FLUSH |
1249 batch->screen->devinfo.ver >= 7 ? PIPE_CONTROL_DATA_CACHE_FLUSH : 0;
8728 PIPE_CONTROL_DATA_CACHE_FLUSH))) {
8821 PIPE_CONTROL_DATA_CACHE_FLUSH;
8838 (flags & PIPE_CONTROL_DATA_CACHE_FLUSH) ? "DC " : "",
8860 pc.DCFlushEnable = flags & PIPE_CONTROL_DATA_CACHE_FLUSH;
  /xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/iris/
iris_pipe_control.c 178 unsigned bits = PIPE_CONTROL_DATA_CACHE_FLUSH | PIPE_CONTROL_CS_STALL;
iris_context.h 211 PIPE_CONTROL_DATA_CACHE_FLUSH = (1 << 19),
221 PIPE_CONTROL_DATA_CACHE_FLUSH | \
iris_state.c 489 PIPE_CONTROL_DATA_CACHE_FLUSH);
542 PIPE_CONTROL_DATA_CACHE_FLUSH |
6203 PIPE_CONTROL_DATA_CACHE_FLUSH)))) {
6270 PIPE_CONTROL_DATA_CACHE_FLUSH;
6280 pc.DCFlushEnable = flags & PIPE_CONTROL_DATA_CACHE_FLUSH;

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