Searched refs:R200_PP_TXCBLEND_0 (Results 1 - 17 of 17) sorted by relevance
| /xsrc/external/mit/MesaLib.old/dist/src/mesa/drivers/dri/r200/ |
| H A D | r200_blit.c | 170 OUT_BATCH_REGVAL(R200_PP_TXCBLEND_0, (R200_TXC_ARG_A_ZERO |
191 OUT_BATCH_REGVAL(R200_PP_TXCBLEND_0, (R200_TXC_ARG_A_ZERO |
225 OUT_BATCH_REGVAL(R200_PP_TXCBLEND_0, (R200_TXC_ARG_A_ZERO |
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| H A D | r200_sanity.c | 88 { R200_PP_TXCBLEND_0, 4, "R200_EMIT_PP_TXCBLEND_0" },
153 { R200_PP_TXCBLEND_0, 32, "R200_PP_AFS_1"},
458 { R200_PP_TXCBLEND_0, "R200_PP_TXCBLEND_0" },
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| H A D | r200_state_init.c | 86 {R200_PP_TXCBLEND_0, 4, "R200_PP_TXCBLEND_0"},
153 {R200_PP_TXCBLEND_0, 32, "R200_PP_AFS_1"},
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| H A D | r200_reg.h | 1132 #define R200_PP_TXCBLEND_0 0x2f00 macro
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| /xsrc/external/mit/MesaLib/dist/src/mesa/drivers/dri/r200/ |
| H A D | r200_blit.c | 157 OUT_BATCH_REGVAL(R200_PP_TXCBLEND_0, (R200_TXC_ARG_A_ZERO |
181 OUT_BATCH_REGVAL(R200_PP_TXCBLEND_0, (R200_TXC_ARG_A_ZERO |
215 OUT_BATCH_REGVAL(R200_PP_TXCBLEND_0, (R200_TXC_ARG_A_ZERO |
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| H A D | r200_sanity.c | 88 { R200_PP_TXCBLEND_0, 4, "R200_EMIT_PP_TXCBLEND_0" },
153 { R200_PP_TXCBLEND_0, 32, "R200_PP_AFS_1"},
458 { R200_PP_TXCBLEND_0, "R200_PP_TXCBLEND_0" },
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| H A D | r200_state_init.c | 86 {R200_PP_TXCBLEND_0, 4, "R200_PP_TXCBLEND_0"},
153 {R200_PP_TXCBLEND_0, 32, "R200_PP_AFS_1"},
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| H A D | r200_reg.h | 1132 #define R200_PP_TXCBLEND_0 0x2f00 macro
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| /xsrc/external/mit/xf86-video-ati/dist/src/ |
| H A D | radeon_render.c | 878 OUT_ACCEL_REG(R200_PP_TXCBLEND_0, R200_TXC_ARG_A_TFACTOR_COLOR |
927 OUT_ACCEL_REG(R200_PP_TXCBLEND_0, R200_TXC_ARG_C_R0_COLOR);
929 OUT_ACCEL_REG(R200_PP_TXCBLEND_0, R200_TXC_ARG_C_ZERO);
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| H A D | radeon_textured_videofuncs.c | 799 OUT_ACCEL_REG(R200_PP_TXCBLEND_0,
900 OUT_ACCEL_REG(R200_PP_TXCBLEND_0,
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| H A D | radeon_exa_render.c | 1115 OUT_ACCEL_REG(R200_PP_TXCBLEND_0, cblend);
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| H A D | radeon_reg.h | 2778 #define R200_PP_TXCBLEND_0 0x2f00 macro
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| /xsrc/external/mit/MesaLib.old/dist/src/mesa/drivers/dri/radeon/ |
| H A D | radeon_state_init.c | 81 {R200_PP_TXCBLEND_0, 4, "R200_PP_TXCBLEND_0"},
148 {R200_PP_TXCBLEND_0, 32, "R200_PP_AFS_1"},
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| /xsrc/external/mit/MesaLib/dist/src/mesa/drivers/dri/radeon/ |
| H A D | radeon_state_init.c | 80 {R200_PP_TXCBLEND_0, 4, "R200_PP_TXCBLEND_0"},
147 {R200_PP_TXCBLEND_0, 32, "R200_PP_AFS_1"},
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| /xsrc/external/mit/xf86-video-ati-kms/dist/src/ |
| H A D | radeon_textured_videofuncs.c | 626 OUT_RING_REG(R200_PP_TXCBLEND_0,
727 OUT_RING_REG(R200_PP_TXCBLEND_0,
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| H A D | radeon_exa_render.c | 1055 OUT_RING_REG(R200_PP_TXCBLEND_0, cblend);
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| H A D | radeon_reg.h | 2778 #define R200_PP_TXCBLEND_0 0x2f00 macro
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