Searched refs:REG_W (Results 1 - 4 of 4) sorted by relevance

/xsrc/external/mit/xf86-video-intel/dist/src/uxa/
H A Di915_3d.h303 #define REG_W(reg) (((reg) >> W_CHANNEL_SHIFT) & REG_CHANNEL_MASK) macro
415 i915_get_hardware_channel_val(REG_W(operand0), \
430 i915_get_hardware_channel_val(REG_W(operand1), \
445 i915_get_hardware_channel_val(REG_W(operand2), \
468 i915_get_hardware_channel_val(REG_W(operand0), \
483 i915_get_hardware_channel_val(REG_W(operand1), \
498 i915_get_hardware_channel_val(REG_W(operand2), \
/xsrc/external/mit/xf86-video-intel-2014/dist/src/uxa/
H A Di915_3d.h303 #define REG_W(reg) (((reg) >> W_CHANNEL_SHIFT) & REG_CHANNEL_MASK) macro
415 i915_get_hardware_channel_val(REG_W(operand0), \
430 i915_get_hardware_channel_val(REG_W(operand1), \
445 i915_get_hardware_channel_val(REG_W(operand2), \
468 i915_get_hardware_channel_val(REG_W(operand0), \
483 i915_get_hardware_channel_val(REG_W(operand1), \
498 i915_get_hardware_channel_val(REG_W(operand2), \
/xsrc/external/mit/xf86-video-intel/dist/src/sna/
H A Dgen3_render.h1150 #define REG_W(reg) (((reg) >> W_CHANNEL_SHIFT) & REG_CHANNEL_MASK) macro
1262 gen3_get_hardware_channel_val(REG_W(operand0), \
1277 gen3_get_hardware_channel_val(REG_W(operand1), \
1292 gen3_get_hardware_channel_val(REG_W(operand2), \
1315 gen3_get_hardware_channel_val(REG_W(operand0), \
1330 gen3_get_hardware_channel_val(REG_W(operand1), \
1345 gen3_get_hardware_channel_val(REG_W(operand2), \
/xsrc/external/mit/xf86-video-intel-2014/dist/src/sna/
H A Dgen3_render.h1150 #define REG_W(reg) (((reg) >> W_CHANNEL_SHIFT) & REG_CHANNEL_MASK) macro
1262 gen3_get_hardware_channel_val(REG_W(operand0), \
1277 gen3_get_hardware_channel_val(REG_W(operand1), \
1292 gen3_get_hardware_channel_val(REG_W(operand2), \
1315 gen3_get_hardware_channel_val(REG_W(operand0), \
1330 gen3_get_hardware_channel_val(REG_W(operand1), \
1345 gen3_get_hardware_channel_val(REG_W(operand2), \

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