Searched refs:REG_X (Results 1 - 4 of 4) sorted by relevance

/xsrc/external/mit/xf86-video-intel/dist/src/uxa/
H A Di915_3d.h300 #define REG_X(reg) (((reg) >> X_CHANNEL_SHIFT) & REG_CHANNEL_MASK) macro
406 OUT_BATCH(i915_get_hardware_channel_val(REG_X(operand0), \
421 i915_get_hardware_channel_val(REG_X(operand1), \
436 i915_get_hardware_channel_val(REG_X(operand2), \
459 OUT_BATCH(i915_get_hardware_channel_val(REG_X(operand0), \
474 i915_get_hardware_channel_val(REG_X(operand1), \
489 i915_get_hardware_channel_val(REG_X(operand2), \
/xsrc/external/mit/xf86-video-intel-2014/dist/src/uxa/
H A Di915_3d.h300 #define REG_X(reg) (((reg) >> X_CHANNEL_SHIFT) & REG_CHANNEL_MASK) macro
406 OUT_BATCH(i915_get_hardware_channel_val(REG_X(operand0), \
421 i915_get_hardware_channel_val(REG_X(operand1), \
436 i915_get_hardware_channel_val(REG_X(operand2), \
459 OUT_BATCH(i915_get_hardware_channel_val(REG_X(operand0), \
474 i915_get_hardware_channel_val(REG_X(operand1), \
489 i915_get_hardware_channel_val(REG_X(operand2), \
/xsrc/external/mit/xf86-video-intel/dist/src/sna/
H A Dgen3_render.h1147 #define REG_X(reg) (((reg) >> X_CHANNEL_SHIFT) & REG_CHANNEL_MASK) macro
1253 OUT_BATCH(gen3_get_hardware_channel_val(REG_X(operand0), \
1268 gen3_get_hardware_channel_val(REG_X(operand1), \
1283 gen3_get_hardware_channel_val(REG_X(operand2), \
1306 OUT_BATCH(gen3_get_hardware_channel_val(REG_X(operand0), \
1321 gen3_get_hardware_channel_val(REG_X(operand1), \
1336 gen3_get_hardware_channel_val(REG_X(operand2), \
/xsrc/external/mit/xf86-video-intel-2014/dist/src/sna/
H A Dgen3_render.h1147 #define REG_X(reg) (((reg) >> X_CHANNEL_SHIFT) & REG_CHANNEL_MASK) macro
1253 OUT_BATCH(gen3_get_hardware_channel_val(REG_X(operand0), \
1268 gen3_get_hardware_channel_val(REG_X(operand1), \
1283 gen3_get_hardware_channel_val(REG_X(operand2), \
1306 OUT_BATCH(gen3_get_hardware_channel_val(REG_X(operand0), \
1321 gen3_get_hardware_channel_val(REG_X(operand1), \
1336 gen3_get_hardware_channel_val(REG_X(operand2), \

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