Searched refs:SI_SH_REG_OFFSET (Results 1 - 22 of 22) sorted by relevance

/xsrc/external/mit/MesaLib/dist/src/amd/vulkan/
H A Dradv_cs.h100 assert(reg >= SI_SH_REG_OFFSET && reg < SI_SH_REG_END);
104 radeon_emit(cs, (reg - SI_SH_REG_OFFSET) >> 2);
118 assert(reg >= SI_SH_REG_OFFSET && reg < SI_SH_REG_END);
127 radeon_emit(cs, (reg - SI_SH_REG_OFFSET) >> 2 | (idx << 28));
H A Dradv_private.h1620 radeon_emit(cs, (sh_offset - SI_SH_REG_OFFSET) >> 2);
H A Dradv_cmd_buffer.c5993 vertex_offset_reg = (base_reg - SI_SH_REG_OFFSET) >> 2;
5995 start_instance_reg = ((base_reg + (draw_id_enable ? 8 : 4)) - SI_SH_REG_OFFSET) >> 2;
5997 draw_id_reg = ((base_reg + 4) - SI_SH_REG_OFFSET) >> 2;
/xsrc/external/mit/MesaLib.old/dist/src/amd/vulkan/
H A Dradv_cs.h86 assert(reg >= SI_SH_REG_OFFSET && reg < SI_SH_REG_END);
90 radeon_emit(cs, (reg - SI_SH_REG_OFFSET) >> 2);
H A Dradv_cmd_buffer.c3624 radeon_emit(cs, (base_reg - SI_SH_REG_OFFSET) >> 2);
3625 radeon_emit(cs, ((base_reg + 4) - SI_SH_REG_OFFSET) >> 2);
3632 radeon_emit(cs, (base_reg - SI_SH_REG_OFFSET) >> 2);
3633 radeon_emit(cs, ((base_reg + 4) - SI_SH_REG_OFFSET) >> 2);
3634 radeon_emit(cs, (((base_reg + 8) - SI_SH_REG_OFFSET) >> 2) |
H A Dradv_private.h1247 radeon_emit(cs, (sh_offset - SI_SH_REG_OFFSET) >> 2);
/xsrc/external/mit/MesaLib/dist/src/gallium/drivers/radeonsi/
H A Dsi_pm4.c61 } else if (reg >= SI_SH_REG_OFFSET && reg < SI_SH_REG_END) {
63 reg -= SI_SH_REG_OFFSET;
H A Dsi_cp_reg_shadowing.c54 offset = SI_SH_REG_OFFSET;
H A Dsi_build_pm4.h115 assert((reg) >= SI_SH_REG_OFFSET && (reg) < SI_SH_REG_END); \
117 radeon_emit(((reg) - SI_SH_REG_OFFSET) >> 2); \
H A Dsi_state_draw.cpp1437 radeon_emit((sh_base_reg + SI_SGPR_BASE_VERTEX * 4 - SI_SH_REG_OFFSET) >> 2);
1438 radeon_emit((sh_base_reg + SI_SGPR_START_INSTANCE * 4 - SI_SH_REG_OFFSET) >> 2);
1455 radeon_emit((sh_base_reg + SI_SGPR_BASE_VERTEX * 4 - SI_SH_REG_OFFSET) >> 2);
1456 radeon_emit((sh_base_reg + SI_SGPR_START_INSTANCE * 4 - SI_SH_REG_OFFSET) >> 2);
1457 radeon_emit(((sh_base_reg + SI_SGPR_DRAWID * 4 - SI_SH_REG_OFFSET) >> 2) |
/xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/r600/
H A Dr600d_common.h31 #define SI_SH_REG_OFFSET 0x0000B000 macro
H A Dr600_cs.h172 assert(reg >= SI_SH_REG_OFFSET && reg < SI_SH_REG_END);
175 radeon_emit(cs, (reg - SI_SH_REG_OFFSET) >> 2);
/xsrc/external/mit/MesaLib/dist/src/gallium/drivers/r600/
H A Dr600d_common.h31 #define SI_SH_REG_OFFSET 0x0000B000 macro
H A Dr600_cs.h172 assert(reg >= SI_SH_REG_OFFSET && reg < SI_SH_REG_END);
175 radeon_emit(cs, (reg - SI_SH_REG_OFFSET) >> 2);
/xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/radeonsi/
H A Dsi_build_pm4.h76 assert(reg >= SI_SH_REG_OFFSET && reg < SI_SH_REG_END);
79 radeon_emit(cs, (reg - SI_SH_REG_OFFSET) >> 2);
H A Dsi_pm4.c58 } else if (reg >= SI_SH_REG_OFFSET && reg < SI_SH_REG_END) {
60 reg -= SI_SH_REG_OFFSET;
H A Dsi_state_draw.c778 radeon_emit(cs, (sh_base_reg + SI_SGPR_BASE_VERTEX * 4 - SI_SH_REG_OFFSET) >> 2);
779 radeon_emit(cs, (sh_base_reg + SI_SGPR_START_INSTANCE * 4 - SI_SH_REG_OFFSET) >> 2);
799 radeon_emit(cs, (sh_base_reg + SI_SGPR_BASE_VERTEX * 4 - SI_SH_REG_OFFSET) >> 2);
800 radeon_emit(cs, (sh_base_reg + SI_SGPR_START_INSTANCE * 4 - SI_SH_REG_OFFSET) >> 2);
801 radeon_emit(cs, ((sh_base_reg + SI_SGPR_DRAWID * 4 - SI_SH_REG_OFFSET) >> 2) |
H A Dsi_descriptors.c2100 radeon_emit(cs, (sh_offset - SI_SH_REG_OFFSET) >> 2);
/xsrc/external/mit/MesaLib/dist/src/amd/common/
H A Dsid.h32 #define SI_SH_REG_OFFSET 0x0000B000 macro
42 #define SI_SH_REG_SPACE_SIZE (SI_SH_REG_END - SI_SH_REG_OFFSET)
H A Dac_debug.c292 ac_parse_set_reg_packet(f, count, SI_SH_REG_OFFSET, ib);
/xsrc/external/mit/MesaLib.old/dist/src/amd/common/
H A Dac_debug.c260 ac_parse_set_reg_packet(f, count, SI_SH_REG_OFFSET, ib);
H A Dsid.h30 #define SI_SH_REG_OFFSET 0x0000B000 macro

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