Searched refs:amdinfo (Results 1 - 14 of 14) sorted by relevance

/xsrc/external/mit/MesaLib.old/dist/src/amd/vulkan/winsys/amdgpu/
H A Dradv_amdgpu_winsys.h43 struct amdgpu_gpu_info amdinfo; member in struct:radv_amdgpu_winsys
H A Dradv_amdgpu_winsys.c45 if (!ac_query_gpu_info(fd, ws->dev, &ws->info, &ws->amdinfo))
52 ws->addrlib = amdgpu_addr_create(&ws->info, &ws->amdinfo, &ws->info.max_alignment);
/xsrc/external/mit/MesaLib/dist/src/amd/vulkan/winsys/amdgpu/
H A Dradv_amdgpu_winsys.h43 struct amdgpu_gpu_info amdinfo; member in struct:radv_amdgpu_winsys
H A Dradv_amdgpu_winsys.c44 if (!ac_query_gpu_info(fd, ws->dev, &ws->info, &ws->amdinfo))
/xsrc/external/mit/MesaLib.old/dist/src/gallium/winsys/amdgpu/drm/
H A Damdgpu_winsys.h78 struct amdgpu_gpu_info amdinfo; member in struct:amdgpu_winsys
H A Damdgpu_winsys.c92 if (!ac_query_gpu_info(fd, ws->dev, &ws->info, &ws->amdinfo))
101 ws->addrlib = amdgpu_addr_create(&ws->info, &ws->amdinfo, &ws->info.max_alignment);
/xsrc/external/mit/MesaLib.old/dist/src/amd/common/
H A Dac_gpu_info.c97 struct amdgpu_gpu_info *amdinfo)
122 r = amdgpu_query_gpu_info(dev, amdinfo);
300 info->pci_id = amdinfo->asic_id; /* TODO: is this correct? */
301 info->vce_harvest_config = amdinfo->vce_harvest_config;
318 if (info->family == CHIP_RAVEN && amdinfo->chip_rev >= 0x8) {
344 !(amdinfo->ids_flags & AMDGPU_IDS_FLAGS_FUSION);
358 info->max_shader_clock = amdinfo->max_engine_clk / 1000;
360 info->max_se = amdinfo->num_shader_engines;
361 info->max_sh_per_se = amdinfo->num_shader_arrays_per_engine;
401 info->num_render_backends = amdinfo
95 ac_query_gpu_info(int fd,amdgpu_device_handle dev,struct radeon_info * info,struct amdgpu_gpu_info * amdinfo) argument
[all...]
H A Dac_gpu_info.h155 struct amdgpu_gpu_info *amdinfo);
H A Dac_surface.h259 const struct amdgpu_gpu_info *amdinfo,
H A Dac_surface.c175 const struct amdgpu_gpu_info *amdinfo,
188 regValue.gbAddrConfig = amdinfo->gb_addr_cfg;
199 regValue.noOfBanks = amdinfo->mc_arb_ramcfg & 0x3;
200 regValue.noOfRanks = (amdinfo->mc_arb_ramcfg & 0x4) >> 2;
202 regValue.backendDisables = amdinfo->enabled_rb_pipes_mask;
203 regValue.pTileConfig = amdinfo->gb_tile_mode;
204 regValue.noOfEntries = ARRAY_SIZE(amdinfo->gb_tile_mode);
209 regValue.pMacroTileConfig = amdinfo->gb_macro_tile_mode;
210 regValue.noOfMacroEntries = ARRAY_SIZE(amdinfo->gb_macro_tile_mode);
174 amdgpu_addr_create(const struct radeon_info * info,const struct amdgpu_gpu_info * amdinfo,uint64_t * max_alignment) argument
/xsrc/external/mit/MesaLib/dist/src/amd/common/
H A Dac_gpu_info.c301 struct amdgpu_gpu_info *amdinfo)
307 if (amdinfo->ids_flags & AMDGPU_IDS_FLAGS_TMZ)
334 struct amdgpu_gpu_info *amdinfo)
363 r = amdgpu_query_gpu_info(dev, amdinfo);
558 info->pci_id = amdinfo->asic_id; /* TODO: is this correct? */
559 info->pci_rev_id = amdinfo->pci_rev_id;
560 info->vce_harvest_config = amdinfo->vce_harvest_config;
563 if (ASICREV_IS(amdinfo->chip_external_rev, asic)) { \
569 switch (amdinfo->family_id) {
631 amdinfo
299 has_tmz_support(amdgpu_device_handle dev,struct radeon_info * info,struct amdgpu_gpu_info * amdinfo) argument
333 ac_query_gpu_info(int fd,void * dev_p,struct radeon_info * info,struct amdgpu_gpu_info * amdinfo) argument
[all...]
H A Dac_gpu_info.h234 struct amdgpu_gpu_info *amdinfo);
/xsrc/external/mit/MesaLib/dist/src/gallium/winsys/amdgpu/drm/
H A Damdgpu_winsys.h96 struct amdgpu_gpu_info amdinfo; member in struct:amdgpu_winsys
H A Damdgpu_winsys.c96 if (!ac_query_gpu_info(fd, ws->dev, &ws->info, &ws->amdinfo))

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