Searched refs:bits3 (Results 1 - 15 of 15) sorted by relevance

/xsrc/external/mit/xf86-video-intel/dist/src/sna/brw/
H A Dbrw_disasm.c673 format(file, "0x%08xUD", inst->bits3.ud);
676 format(file, "%dD", inst->bits3.d);
679 format(file, "0x%04xUW", (uint16_t) inst->bits3.ud);
682 format(file, "%dW", (int16_t) inst->bits3.d);
685 format(file, "0x%02xUB", (int8_t) inst->bits3.ud);
691 format(file, "0x%08xV", inst->bits3.ud);
694 format(file, "%-gF", inst->bits3.f);
752 if (inst->bits3.da1.src1_address_mode == BRW_ADDRESS_DIRECT) {
756 inst->bits3.da1.src1_vert_stride,
757 inst->bits3
[all...]
H A Dbrw_eu_emit.c252 insn->bits3.ud = reg.dw1.ud;
318 insn->bits3.da1.src1_abs = reg.abs;
319 insn->bits3.da1.src1_negate = reg.negate;
325 insn->bits3.ud = reg.dw1.ud;
334 insn->bits3.da1.src1_subreg_nr = reg.subnr;
335 insn->bits3.da1.src1_reg_nr = reg.nr;
337 insn->bits3.da16.src1_subreg_nr = reg.subnr / 16;
338 insn->bits3.da16.src1_reg_nr = reg.nr;
344 insn->bits3.da1.src1_horiz_stride = BRW_HORIZONTAL_STRIDE_0;
345 insn->bits3
[all...]
H A Dbrw_eu.h698 * 27:24 of the header (destreg__conditionalmod); EOT is in bits3.
1118 } bits3; member in struct:brw_instruction
/xsrc/external/mit/xf86-video-intel-2014/dist/src/sna/brw/
H A Dbrw_disasm.c673 format(file, "0x%08xUD", inst->bits3.ud);
676 format(file, "%dD", inst->bits3.d);
679 format(file, "0x%04xUW", (uint16_t) inst->bits3.ud);
682 format(file, "%dW", (int16_t) inst->bits3.d);
685 format(file, "0x%02xUB", (int8_t) inst->bits3.ud);
691 format(file, "0x%08xV", inst->bits3.ud);
694 format(file, "%-gF", inst->bits3.f);
752 if (inst->bits3.da1.src1_address_mode == BRW_ADDRESS_DIRECT) {
756 inst->bits3.da1.src1_vert_stride,
757 inst->bits3
[all...]
H A Dbrw_eu_emit.c252 insn->bits3.ud = reg.dw1.ud;
318 insn->bits3.da1.src1_abs = reg.abs;
319 insn->bits3.da1.src1_negate = reg.negate;
325 insn->bits3.ud = reg.dw1.ud;
334 insn->bits3.da1.src1_subreg_nr = reg.subnr;
335 insn->bits3.da1.src1_reg_nr = reg.nr;
337 insn->bits3.da16.src1_subreg_nr = reg.subnr / 16;
338 insn->bits3.da16.src1_reg_nr = reg.nr;
344 insn->bits3.da1.src1_horiz_stride = BRW_HORIZONTAL_STRIDE_0;
345 insn->bits3
[all...]
H A Dbrw_eu.h698 * 27:24 of the header (destreg__conditionalmod); EOT is in bits3.
1118 } bits3; member in struct:brw_instruction
/xsrc/external/mit/xf86-video-intel/dist/src/uxa/
H A Dbrw_structs.h426 } bits3; member in struct:brw_state_base_address
1384 } bits3; member in struct:brw_instruction
/xsrc/external/mit/xf86-video-intel/dist/xvmc/
H A Dbrw_structs.h426 } bits3; member in struct:brw_state_base_address
1384 } bits3; member in struct:brw_instruction
/xsrc/external/mit/xf86-video-intel-2014/dist/src/uxa/
H A Dbrw_structs.h426 } bits3; member in struct:brw_state_base_address
1384 } bits3; member in struct:brw_instruction
/xsrc/external/mit/xf86-video-intel-2014/dist/xvmc/
H A Dbrw_structs.h426 } bits3; member in struct:brw_state_base_address
1384 } bits3; member in struct:brw_instruction
/xsrc/external/mit/xf86-video-intel-old/dist/src/
H A Dbrw_structs.h426 } bits3; member in struct:brw_state_base_address
1379 } bits3; member in struct:brw_instruction
/xsrc/external/mit/xf86-video-intel/dist/src/sna/
H A Dgen4_render.h1441 } bits3; member in struct:gen4_state_base_address
2447 } bits3; member in struct:gen4_instruction
H A Dgen5_render.h1529 } bits3; member in struct:gen5_state_base_address
2527 } bits3; member in struct:gen5_instruction
/xsrc/external/mit/xf86-video-intel-2014/dist/src/sna/
H A Dgen4_render.h1441 } bits3; member in struct:gen4_state_base_address
2447 } bits3; member in struct:gen4_instruction
H A Dgen5_render.h1529 } bits3; member in struct:gen5_state_base_address
2527 } bits3; member in struct:gen5_instruction

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