| /xsrc/external/mit/MesaLib/dist/src/panfrost/midgard/ |
| midgard_opt_dce.c | 87 unsigned cmask = mir_from_bytemask(rounded, type_size); local
89 ins->mask &= cmask;
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| mir.c | 272 unsigned cmask = 0; local
276 cmask |= (1 << swizzle[c]);
279 return pan_to_bytemask(bits, cmask);
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| /xsrc/external/mit/MesaLib/dist/src/gallium/drivers/nouveau/nv30/ |
| nv30_state.c | 44 uint32_t blend[2], cmask[2]; local
65 cmask[0] = !!(cso->rt[0].colormask & PIPE_MASK_A) << 24 |
71 cmask[1] = 0;
74 cmask[1] |= !!(cso->rt[i].colormask & PIPE_MASK_A) << (0 + (i * 4)) |
81 cmask[1] = 0x00001110 * !!(cmask[0] & 0x01000000);
82 cmask[1] |= 0x00002220 * !!(cmask[0] & 0x00010000);
83 cmask[1] |= 0x00004440 * !!(cmask[0] & 0x00000100)
[all...] |
| /xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/nouveau/nv30/ |
| nv30_state.c | 44 uint32_t blend[2], cmask[2]; local
65 cmask[0] = !!(cso->rt[0].colormask & PIPE_MASK_A) << 24 |
71 cmask[1] = 0;
74 cmask[1] |= !!(cso->rt[i].colormask & PIPE_MASK_A) << (0 + (i * 4)) |
81 cmask[1] = 0x00001110 * !!(cmask[0] & 0x01000000);
82 cmask[1] |= 0x00002220 * !!(cmask[0] & 0x00010000);
83 cmask[1] |= 0x00004440 * !!(cmask[0] & 0x00000100)
[all...] |
| /xsrc/external/mit/MesaLib/dist/src/gallium/drivers/r600/ |
| r600_texture.c | 73 /* CMASK as:
75 * dst: If overwriting the whole texture, discard CMASK and use
78 if (rdst->cmask.size && rdst->dirty_level_mask & (1 << dst_level)) {
79 /* The CMASK clear is only enabled for the first level. */
90 if (rsrc->cmask.size && rsrc->dirty_level_mask & (1 << src_level))
335 if (!rtex->cmask.size)
340 /* Disable CMASK. */
341 memset(&rtex->cmask, 0, sizeof(rtex->cmask));
342 rtex->cmask.base_address_reg = rtex->resource.gpu_address >> 8
[all...] |
| r600_blit.c | 132 * There is also a hardlock if CMASK and FMASK are not present.
394 assert(tex->cmask.size);
418 assert(tex->cmask.size);
458 } else if (rtex->cmask.size) {
864 (!dst->cmask.size || !dst->dirty_level_mask) /* dst cannot be fast-cleared */) {
972 if (!rtex->is_depth && rtex->cmask.size) {
|
| r600_state.c | 963 if (rtex->cmask.size) {
964 surf->cb_color_cmask = rtex->cmask.offset >> 8;
965 surf->cb_color_mask |= S_028100_CMASK_BLOCK_MAX(rtex->cmask.slice_tile_max);
971 } else { /* cmask only */
975 /* Allocate dummy FMASK and CMASK if they aren't allocated already.
977 * R6xx needs FMASK and CMASK for the destination buffer of color resolve,
978 * otherwise it hangs. We don't have FMASK and CMASK pre-allocated,
981 struct r600_cmask_info cmask; local
984 r600_texture_get_cmask_info(&rscreen->b, rtex, &cmask);
987 /* CMASK. *
[all...] |
| r600_pipe_common.h | 220 struct r600_cmask_info cmask; member in struct:r600_texture
271 struct r600_resource *cb_buffer_cmask; /* Used for CMASK relocations. R600 only */
|
| r600_state_common.c | 697 if (!is_buffer && rtex->cmask.size) {
752 if (rtex->cmask.size) {
804 if (rtex->cmask.size) {
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| /xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/r600/ |
| r600_texture.c | 72 /* CMASK as:
74 * dst: If overwriting the whole texture, discard CMASK and use
77 if (rdst->cmask.size && rdst->dirty_level_mask & (1 << dst_level)) {
78 /* The CMASK clear is only enabled for the first level. */
89 if (rsrc->cmask.size && rsrc->dirty_level_mask & (1 << src_level))
336 if (!rtex->cmask.size)
341 /* Disable CMASK. */
342 memset(&rtex->cmask, 0, sizeof(rtex->cmask));
343 rtex->cmask.base_address_reg = rtex->resource.gpu_address >> 8
[all...] |
| r600_blit.c | 132 * There is also a hardlock if CMASK and FMASK are not present.
394 assert(tex->cmask.size);
418 assert(tex->cmask.size);
458 } else if (rtex->cmask.size) {
862 (!dst->cmask.size || !dst->dirty_level_mask) /* dst cannot be fast-cleared */) {
970 if (!rtex->is_depth && rtex->cmask.size) {
|
| r600_state.c | 960 if (rtex->cmask.size) {
961 surf->cb_color_cmask = rtex->cmask.offset >> 8;
962 surf->cb_color_mask |= S_028100_CMASK_BLOCK_MAX(rtex->cmask.slice_tile_max);
968 } else { /* cmask only */
972 /* Allocate dummy FMASK and CMASK if they aren't allocated already.
974 * R6xx needs FMASK and CMASK for the destination buffer of color resolve,
975 * otherwise it hangs. We don't have FMASK and CMASK pre-allocated,
978 struct r600_cmask_info cmask; local
981 r600_texture_get_cmask_info(&rscreen->b, rtex, &cmask);
984 /* CMASK. *
[all...] |
| r600_pipe_common.h | 224 struct r600_cmask_info cmask; member in struct:r600_texture
275 struct r600_resource *cb_buffer_cmask; /* Used for CMASK relocations. R600 only */
|
| r600_state_common.c | 672 if (!is_buffer && rtex->cmask.size) {
722 if (rtex->cmask.size) {
774 if (rtex->cmask.size) {
|
| /xsrc/external/mit/MesaLib/dist/src/broadcom/vulkan/ |
| v3dv_meta_copy.c | 433 VkColorComponentFlags cmask,
471 VkColorComponentFlags cmask = 0; /* All components */ local
510 cmask = VK_COLOR_COMPONENT_R_BIT |
720 cmask, &cswizzle,
1538 VkColorComponentFlags cmask,
1550 *p = cmask;
1802 VkColorComponentFlags cmask,
1830 .colorWriteMask = cmask,
1864 VkColorComponentFlags cmask,
1873 get_texel_buffer_copy_pipeline_cache_key(format, cmask, cswizzle, is_layered
2525 VkColorComponentFlags cmask = 0; \/* Write all components *\/ local
[all...] |
| /xsrc/external/mit/MesaLib/dist/src/compiler/nir/ |
| nir_lower_alu.c | 152 nir_ssa_def *cmask = nir_imm_intN_t(b, (1ull << (src0->bit_size / 2)) - 1, src0->bit_size); local
170 nir_ssa_def *src0l = nir_iand(b, src0, cmask);
171 nir_ssa_def *src1l = nir_iand(b, src1, cmask);
|
| /xsrc/external/mit/MesaLib.old/dist/src/amd/vulkan/ |
| radv_image.c | 671 fmask_state[5] |= S_008F24_META_PIPE_ALIGNED(image->planes[0].surface.u.gfx9.cmask.pipe_aligned) |
672 S_008F24_META_RB_ALIGNED(image->planes[0].surface.u.gfx9.cmask.rb_aligned);
845 /* Each element of CMASK is a nibble. */
862 radv_image_get_cmask_info(device, image, &image->cmask);
864 if (!image->cmask.size)
867 assert(image->cmask.alignment);
869 image->cmask.offset = align64(image->size, image->cmask.alignment);
872 image->clear_value_offset = image->cmask.offset + image->cmask.size
[all...] |
| radv_private.h | 1533 struct radv_cmask_info cmask; member in struct:radv_image
1578 * Return whether the image has CMASK metadata for color surfaces.
1583 return image->cmask.size;
|
| radv_meta_clear.c | 925 /* RB+ doesn't work with CMASK fast clear on Stoney. */
1307 * CMASK metadata.
1310 /* DCC fast clear with MSAA should clear CMASK to 0xC. */
1322 image->offset + image->cmask.offset,
1323 image->cmask.size, value);
1468 /* DCC fast clear with MSAA should clear CMASK. */
1507 /* clear cmask buffer */
|
| /xsrc/external/mit/MesaLib.old/dist/src/amd/common/ |
| ac_surface.h | 144 struct gfx9_surf_meta_flags cmask; /* metadata of fmask */ member in struct:gfx9_surf_layout
204 * - CMASK if it's TC-compatible or if the gen is GFX9
|
| ac_surface.c | 600 /* Each element of CMASK is a nibble. */
1024 /* The rotated micro tile mode doesn't work if both CMASK and RB+ are
1112 /* CMASK fast clear uses these even if FMASK isn't allocated.
1416 /* CMASK */
1447 surf->u.gfx9.cmask.rb_aligned = cin.cMaskFlags.rbAligned;
1448 surf->u.gfx9.cmask.pipe_aligned = cin.cMaskFlags.pipeAligned;
1553 /* This is propagated to HTILE/DCC/CMASK. */
1690 /* The rotated micro tile mode doesn't work if both CMASK and RB+ are
|
| /xsrc/external/mit/xorg-server.old/dist/dix/ |
| colormap.c | 2276 Pixel bits, base, cmask, rgbbad; local
2291 cmask = pmap->pVisual->redMask;
2294 numents = (cmask >> offset) + 1;
2299 cmask = pmap->pVisual->greenMask;
2302 numents = (cmask >> offset) + 1;
2307 cmask = pmap->pVisual->blueMask;
2310 numents = (cmask >> offset) + 1;
2316 cmask = ~((Pixel)0);
2332 pixTest = ((*pptr | bits) & cmask) >> offset;
|
| /xsrc/external/mit/xorg-server/dist/dix/ |
| colormap.c | 2124 Pixel bits, base, cmask, rgbbad; local
2138 cmask = pmap->pVisual->redMask;
2141 numents = (cmask >> offset) + 1;
2146 cmask = pmap->pVisual->greenMask;
2149 numents = (cmask >> offset) + 1;
2154 cmask = pmap->pVisual->blueMask;
2157 numents = (cmask >> offset) + 1;
2163 cmask = ~((Pixel) 0);
2176 pixTest = ((*pptr | bits) & cmask) >> offset;
|
| /xsrc/external/mit/MesaLib/dist/src/amd/common/ |
| ac_surface.c | 932 /* Each element of CMASK is a nibble. */
1338 /* The rotated micro tile mode doesn't work if both CMASK and RB+ are
1587 ADDR2_COMPUTE_CMASK_INFO_OUTPUT *cmask,
1590 equation->meta_block_width = cmask->metaBlkWidth;
1591 equation->meta_block_height = cmask->metaBlkHeight;
1595 assert(cmask->equation.gfx9.num_bits <= ARRAY_SIZE(equation->u.gfx9.bit));
1597 equation->u.gfx9.num_bits = cmask->equation.gfx9.num_bits;
1598 equation->u.gfx9.num_pipe_bits = cmask->equation.gfx9.numPipeBits;
1601 equation->u.gfx9.bit[b].coord[c].dim = cmask->equation.gfx9.bit[b].coord[c].dim;
1602 equation->u.gfx9.bit[b].coord[c].ord = cmask->equation.gfx9.bit[b].coord[c].ord
[all...] |
| /xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/svga/ |
| svga_tgsi_vgpu10.c | 3459 unsigned cmask = plane_mask & VGPU10_OPERAND_4_COMPONENT_MASK_ALL; local
3461 VGPU10_NAME_CLIP_DISTANCE, cmask);
3465 unsigned cmask = (plane_mask >> 4) & VGPU10_OPERAND_4_COMPONENT_MASK_ALL; local
3467 VGPU10_NAME_CLIP_DISTANCE, cmask);
|
