Searched refs:da16 (Results 1 - 15 of 15) sorted by relevance

/xsrc/external/mit/xf86-video-intel/dist/src/sna/brw/
H A Dbrw_disasm.c545 if (inst->bits1.da16.dest_address_mode == BRW_ADDRESS_DIRECT) {
546 if (reg(file, inst->bits1.da16.dest_reg_file, inst->bits1.da16.dest_reg_nr))
549 if (inst->bits1.da16.dest_subreg_nr)
550 format(file, ".%d", inst->bits1.da16.dest_subreg_nr /
551 reg_type_size[inst->bits1.da16.dest_reg_type]);
553 control(file, "writemask", writemask, inst->bits1.da16.dest_writemask, NULL);
554 control(file, "dest reg encoding", reg_encoding, inst->bits1.da16.dest_reg_type, NULL);
666 control(file, "src da16 reg type", reg_encoding, _reg_type, NULL);
728 if (inst->bits2.da16
[all...]
H A Dbrw_eu_emit.c122 insn->bits1.da16.dest_subreg_nr = dest.subnr / 16;
123 insn->bits1.da16.dest_writemask = dest.dw1.bits.writemask;
124 /* even ignored in da16, still need to set as '01' */
125 insn->bits1.da16.dest_horiz_stride = 1;
140 /* even ignored in da16, still need to set as '01' */
264 insn->bits2.da16.src0_subreg_nr = reg.subnr / 16;
265 insn->bits2.da16.src0_reg_nr = reg.nr;
289 insn->bits2.da16.src0_swz_x = BRW_GET_SWZ(reg.dw1.bits.swizzle, BRW_CHANNEL_X);
290 insn->bits2.da16.src0_swz_y = BRW_GET_SWZ(reg.dw1.bits.swizzle, BRW_CHANNEL_Y);
291 insn->bits2.da16
[all...]
H A Dbrw_eu.h587 } da16; member in union:brw_instruction::__anon0c137b5d020a
676 } da16; member in union:brw_instruction::__anon0c137b5d090a
745 } da16; member in union:brw_instruction::__anon0c137b5d100a
/xsrc/external/mit/xf86-video-intel-2014/dist/src/sna/brw/
H A Dbrw_disasm.c545 if (inst->bits1.da16.dest_address_mode == BRW_ADDRESS_DIRECT) {
546 if (reg(file, inst->bits1.da16.dest_reg_file, inst->bits1.da16.dest_reg_nr))
549 if (inst->bits1.da16.dest_subreg_nr)
550 format(file, ".%d", inst->bits1.da16.dest_subreg_nr /
551 reg_type_size[inst->bits1.da16.dest_reg_type]);
553 control(file, "writemask", writemask, inst->bits1.da16.dest_writemask, NULL);
554 control(file, "dest reg encoding", reg_encoding, inst->bits1.da16.dest_reg_type, NULL);
666 control(file, "src da16 reg type", reg_encoding, _reg_type, NULL);
728 if (inst->bits2.da16
[all...]
H A Dbrw_eu_emit.c122 insn->bits1.da16.dest_subreg_nr = dest.subnr / 16;
123 insn->bits1.da16.dest_writemask = dest.dw1.bits.writemask;
124 /* even ignored in da16, still need to set as '01' */
125 insn->bits1.da16.dest_horiz_stride = 1;
140 /* even ignored in da16, still need to set as '01' */
264 insn->bits2.da16.src0_subreg_nr = reg.subnr / 16;
265 insn->bits2.da16.src0_reg_nr = reg.nr;
289 insn->bits2.da16.src0_swz_x = BRW_GET_SWZ(reg.dw1.bits.swizzle, BRW_CHANNEL_X);
290 insn->bits2.da16.src0_swz_y = BRW_GET_SWZ(reg.dw1.bits.swizzle, BRW_CHANNEL_Y);
291 insn->bits2.da16
[all...]
H A Dbrw_eu.h587 } da16; member in union:brw_instruction::__anon2bd0c611020a
676 } da16; member in union:brw_instruction::__anon2bd0c611090a
745 } da16; member in union:brw_instruction::__anon2bd0c611100a
/xsrc/external/mit/xf86-video-intel/dist/src/uxa/
H A Dbrw_structs.h1168 } da16; member in union:brw_instruction::__anon375735ed510a
1230 } da16; member in union:brw_instruction::__anon375735ed560a
1280 } da16; member in union:brw_instruction::__anon375735ed5b0a
/xsrc/external/mit/xf86-video-intel/dist/xvmc/
H A Dbrw_structs.h1168 } da16; member in union:brw_instruction::__anon5c4f4f86510a
1230 } da16; member in union:brw_instruction::__anon5c4f4f86560a
1280 } da16; member in union:brw_instruction::__anon5c4f4f865b0a
/xsrc/external/mit/xf86-video-intel-2014/dist/src/uxa/
H A Dbrw_structs.h1168 } da16; member in union:brw_instruction::__anon4ebdd721510a
1230 } da16; member in union:brw_instruction::__anon4ebdd721560a
1280 } da16; member in union:brw_instruction::__anon4ebdd7215b0a
/xsrc/external/mit/xf86-video-intel-2014/dist/xvmc/
H A Dbrw_structs.h1168 } da16; member in union:brw_instruction::__anonbf125d3a510a
1230 } da16; member in union:brw_instruction::__anonbf125d3a560a
1280 } da16; member in union:brw_instruction::__anonbf125d3a5b0a
/xsrc/external/mit/xf86-video-intel-old/dist/src/
H A Dbrw_structs.h1163 } da16; member in union:brw_instruction::__anonfa77c8dc510a
1225 } da16; member in union:brw_instruction::__anonfa77c8dc560a
1275 } da16; member in union:brw_instruction::__anonfa77c8dc5b0a
/xsrc/external/mit/xf86-video-intel/dist/src/sna/
H A Dgen4_render.h2231 } da16; member in union:gen4_instruction::__anon5ecad36c510a
2293 } da16; member in union:gen4_instruction::__anon5ecad36c560a
2343 } da16; member in union:gen4_instruction::__anon5ecad36c5b0a
H A Dgen5_render.h2311 } da16; member in union:gen5_instruction::__anon62d5648d510a
2373 } da16; member in union:gen5_instruction::__anon62d5648d560a
2423 } da16; member in union:gen5_instruction::__anon62d5648d5b0a
/xsrc/external/mit/xf86-video-intel-2014/dist/src/sna/
H A Dgen4_render.h2231 } da16; member in union:gen4_instruction::__anon763174a0510a
2293 } da16; member in union:gen4_instruction::__anon763174a0560a
2343 } da16; member in union:gen4_instruction::__anon763174a05b0a
H A Dgen5_render.h2311 } da16; member in union:gen5_instruction::__anon7a3c05c1510a
2373 } da16; member in union:gen5_instruction::__anon7a3c05c1560a
2423 } da16; member in union:gen5_instruction::__anon7a3c05c15b0a

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