Searched refs:db_depth_base (Results 1 - 10 of 10) sorted by relevance

/xsrc/external/mit/MesaLib/dist/src/gallium/drivers/radeonsi/
H A Dsi_state.c2563 surf->db_depth_base = tex->buffer.gpu_address >> 8;
2604 surf->db_depth_base =
3310 radeon_emit(zb->db_depth_base); /* DB_Z_READ_BASE */
3312 radeon_emit(zb->db_depth_base); /* DB_Z_WRITE_BASE */
3316 radeon_emit(zb->db_depth_base >> 32); /* DB_Z_READ_BASE_HI */
3318 radeon_emit(zb->db_depth_base >> 32); /* DB_Z_WRITE_BASE_HI */
3331 radeon_emit(zb->db_depth_base); /* DB_Z_READ_BASE */
3332 radeon_emit(S_028044_BASE_HI(zb->db_depth_base >> 32)); /* DB_Z_READ_BASE_HI */
3335 radeon_emit(zb->db_depth_base); /* DB_Z_WRITE_BASE */
3336 radeon_emit(S_028054_BASE_HI(zb->db_depth_base >> 3
[all...]
H A Dsi_pipe.h437 uint64_t db_depth_base; /* DB_Z_READ/WRITE_BASE */ member in struct:si_surface
/xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/r600/
H A Dr600_pipe_common.h278 uint64_t db_depth_base; /* DB_Z_READ/WRITE_BASE (EG and later) or DB_DEPTH_BASE (r600) */ member in struct:r600_surface
H A Dr600_state.c1067 surf->db_depth_base = offset >> 8;
1461 radeon_emit(cs, surf->db_depth_base); /* R_02800C_DB_DEPTH_BASE */
H A Devergreen_state.c1399 surf->db_depth_base = offset;
1932 radeon_emit(cs, zb->db_depth_base); /* R_028048_DB_Z_READ_BASE */
1934 radeon_emit(cs, zb->db_depth_base); /* R_028050_DB_Z_WRITE_BASE */
/xsrc/external/mit/MesaLib/dist/src/gallium/drivers/r600/
H A Dr600_pipe_common.h274 uint64_t db_depth_base; /* DB_Z_READ/WRITE_BASE (EG and later) or DB_DEPTH_BASE (r600) */ member in struct:r600_surface
H A Dr600_state.c1070 surf->db_depth_base = offset >> 8;
1464 radeon_emit(cs, surf->db_depth_base); /* R_02800C_DB_DEPTH_BASE */
H A Devergreen_state.c1405 surf->db_depth_base = offset;
1938 radeon_emit(cs, zb->db_depth_base); /* R_028048_DB_Z_READ_BASE */
1940 radeon_emit(cs, zb->db_depth_base); /* R_028050_DB_Z_WRITE_BASE */
/xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/radeonsi/
H A Dsi_state.c2547 surf->db_depth_base = tex->buffer.gpu_address >> 8;
2600 surf->db_depth_base = (tex->buffer.gpu_address +
3227 radeon_emit(cs, zb->db_depth_base); /* DB_Z_READ_BASE */
3228 radeon_emit(cs, S_028044_BASE_HI(zb->db_depth_base >> 32)); /* DB_Z_READ_BASE_HI */
3231 radeon_emit(cs, zb->db_depth_base); /* DB_Z_WRITE_BASE */
3232 radeon_emit(cs, S_028054_BASE_HI(zb->db_depth_base >> 32)); /* DB_Z_WRITE_BASE_HI */
3247 radeon_emit(cs, zb->db_depth_base); /* DB_Z_READ_BASE */
3249 radeon_emit(cs, zb->db_depth_base); /* DB_Z_WRITE_BASE */
H A Dsi_pipe.h376 uint64_t db_depth_base; /* DB_Z_READ/WRITE_BASE */ member in struct:si_surface

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