| /xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/r600/ |
| H A D | r600_pipe_common.h | 280 uint64_t db_htile_data_base; member in struct:r600_surface
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| H A D | r600_state.c | 1074 surf->db_htile_data_base = rtex->htile_offset >> 8;
1559 radeon_set_context_reg(cs, R_028014_DB_HTILE_DATA_BASE, a->rsurf->db_htile_data_base);
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| H A D | evergreen_state.c | 1430 surf->db_htile_data_base = va >> 8;
2058 radeon_set_context_reg(cs, R_028014_DB_HTILE_DATA_BASE, a->rsurf->db_htile_data_base);
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| /xsrc/external/mit/MesaLib/dist/src/gallium/drivers/r600/ |
| H A D | r600_pipe_common.h | 276 uint64_t db_htile_data_base; member in struct:r600_surface
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| H A D | r600_state.c | 1077 surf->db_htile_data_base = rtex->htile_offset >> 8;
1562 radeon_set_context_reg(cs, R_028014_DB_HTILE_DATA_BASE, a->rsurf->db_htile_data_base);
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| H A D | evergreen_state.c | 1436 surf->db_htile_data_base = va >> 8;
2064 radeon_set_context_reg(cs, R_028014_DB_HTILE_DATA_BASE, a->rsurf->db_htile_data_base);
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| /xsrc/external/mit/MesaLib/dist/src/gallium/drivers/radeonsi/ |
| H A D | si_state.c | 2553 surf->db_htile_data_base = 0;
2591 surf->db_htile_data_base = (tex->buffer.gpu_address + tex->surface.meta_offset) >> 8;
2663 surf->db_htile_data_base = (tex->buffer.gpu_address + tex->surface.meta_offset) >> 8;
3302 radeon_set_context_reg(R_028014_DB_HTILE_DATA_BASE, zb->db_htile_data_base);
3320 radeon_emit(zb->db_htile_data_base >> 32); /* DB_HTILE_DATA_BASE_HI */
3323 radeon_emit(zb->db_htile_data_base); /* DB_HTILE_DATA_BASE */
3324 radeon_emit(S_028018_BASE_HI(zb->db_htile_data_base >> 32)); /* DB_HTILE_DATA_BASE_HI */
3360 radeon_set_context_reg(R_028014_DB_HTILE_DATA_BASE, zb->db_htile_data_base);
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| H A D | si_pipe.h | 439 uint64_t db_htile_data_base; member in struct:si_surface
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| /xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/radeonsi/ |
| H A D | si_state.c | 2542 surf->db_htile_data_base = 0;
2588 surf->db_htile_data_base = (tex->buffer.gpu_address +
2666 surf->db_htile_data_base = (tex->buffer.gpu_address +
3219 radeon_emit(cs, zb->db_htile_data_base); /* DB_HTILE_DATA_BASE */
3220 radeon_emit(cs, S_028018_BASE_HI(zb->db_htile_data_base >> 32)); /* DB_HTILE_DATA_BASE_HI */
3240 radeon_set_context_reg(cs, R_028014_DB_HTILE_DATA_BASE, zb->db_htile_data_base);
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| H A D | si_pipe.h | 378 uint64_t db_htile_data_base; member in struct:si_surface
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| /xsrc/external/mit/MesaLib.old/dist/src/amd/vulkan/ |
| H A D | radv_private.h | 1824 uint64_t db_htile_data_base; member in struct:radv_ds_buffer_info
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| H A D | radv_cmd_buffer.c | 1168 radeon_emit(cmd_buffer->cs, ds->db_htile_data_base);
1169 radeon_emit(cmd_buffer->cs, S_028018_BASE_HI(ds->db_htile_data_base >> 32));
1188 radeon_set_context_reg(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, ds->db_htile_data_base);
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| H A D | radv_device.c | 4500 ds->db_htile_data_base = 0;
4542 ds->db_htile_data_base = va >> 8;
4607 ds->db_htile_data_base = va >> 8;
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| /xsrc/external/mit/MesaLib/dist/src/amd/vulkan/ |
| H A D | radv_cmd_buffer.c | 1899 radeon_set_context_reg(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, ds->db_htile_data_base);
1916 radeon_emit(cmd_buffer->cs, ds->db_htile_data_base >> 32);
1919 radeon_emit(cmd_buffer->cs, ds->db_htile_data_base);
1920 radeon_emit(cmd_buffer->cs, S_028018_BASE_HI(ds->db_htile_data_base >> 32));
1943 radeon_set_context_reg(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, ds->db_htile_data_base);
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| H A D | radv_device.c | 6874 ds->db_htile_data_base = radv_buffer_get_va(htile_buffer->bo) >> 8;
6923 ds->db_htile_data_base = 0;
6975 ds->db_htile_data_base = va >> 8;
7044 ds->db_htile_data_base = va >> 8;
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| H A D | radv_private.h | 1268 uint64_t db_htile_data_base; member in struct:radv_ds_buffer_info
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