| /xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/r600/ |
| H A D | r600_pipe_common.h | 288 unsigned db_htile_surface; member in struct:r600_surface
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| H A D | r600_state.c | 1075 surf->db_htile_surface = S_028D24_HTILE_WIDTH(1) |
1553 if (a->rsurf && a->rsurf->db_htile_surface) {
1558 radeon_set_context_reg(cs, R_028D24_DB_HTILE_SURFACE, a->rsurf->db_htile_surface);
1603 if (rctx->db_state.rsurf && rctx->db_state.rsurf->db_htile_surface) {
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| H A D | evergreen_state.c | 1431 surf->db_htile_surface = S_028ABC_HTILE_WIDTH(1) |
2051 if (a->rsurf && a->rsurf->db_htile_surface) {
2056 radeon_set_context_reg(cs, R_028ABC_DB_HTILE_SURFACE, a->rsurf->db_htile_surface);
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| /xsrc/external/mit/MesaLib/dist/src/gallium/drivers/r600/ |
| H A D | r600_pipe_common.h | 284 unsigned db_htile_surface; member in struct:r600_surface
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| H A D | r600_state.c | 1078 surf->db_htile_surface = S_028D24_HTILE_WIDTH(1) |
1556 if (a->rsurf && a->rsurf->db_htile_surface) {
1561 radeon_set_context_reg(cs, R_028D24_DB_HTILE_SURFACE, a->rsurf->db_htile_surface);
1606 if (rctx->db_state.rsurf && rctx->db_state.rsurf->db_htile_surface) {
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| H A D | evergreen_state.c | 1437 surf->db_htile_surface = S_028ABC_HTILE_WIDTH(1) |
2057 if (a->rsurf && a->rsurf->db_htile_surface) {
2062 radeon_set_context_reg(cs, R_028ABC_DB_HTILE_SURFACE, a->rsurf->db_htile_surface);
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| /xsrc/external/mit/MesaLib/dist/src/gallium/drivers/radeonsi/ |
| H A D | si_state.c | 2554 surf->db_htile_surface = 0;
2592 surf->db_htile_surface =
2595 surf->db_htile_surface |= S_028ABC_RB_ALIGNED(1);
2664 surf->db_htile_surface = S_028ABC_FULL_CACHE(1);
3274 unsigned db_htile_surface = zb->db_htile_surface; local in function:si_emit_framebuffer_state
3348 db_htile_surface |= S_028ABC_TC_COMPATIBLE(1);
3381 radeon_set_context_reg(R_028ABC_DB_HTILE_SURFACE, db_htile_surface);
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| H A D | si_pipe.h | 448 unsigned db_htile_surface; member in struct:si_surface
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| /xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/radeonsi/ |
| H A D | si_state.c | 2543 surf->db_htile_surface = 0;
2590 surf->db_htile_surface = S_028ABC_FULL_CACHE(1) |
2668 surf->db_htile_surface = S_028ABC_FULL_CACHE(1);
2671 surf->db_htile_surface |= S_028ABC_TC_COMPATIBLE(1);
3260 radeon_set_context_reg(cs, R_028ABC_DB_HTILE_SURFACE, zb->db_htile_surface);
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| H A D | si_pipe.h | 387 unsigned db_htile_surface; member in struct:si_surface
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| /xsrc/external/mit/MesaLib.old/dist/src/amd/vulkan/ |
| H A D | radv_device.c | 4501 ds->db_htile_surface = 0;
4543 ds->db_htile_surface = S_028ABC_FULL_CACHE(1) |
4608 ds->db_htile_surface = S_028ABC_FULL_CACHE(1);
4614 ds->db_htile_surface |= S_028ABC_TC_COMPATIBLE(1);
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| H A D | radv_private.h | 1831 uint32_t db_htile_surface; member in struct:radv_ds_buffer_info
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| H A D | radv_cmd_buffer.c | 1163 radeon_set_context_reg(cmd_buffer->cs, R_028ABC_DB_HTILE_SURFACE, ds->db_htile_surface);
|
| /xsrc/external/mit/MesaLib/dist/src/amd/vulkan/ |
| H A D | radv_device.c | 6875 ds->db_htile_surface = S_028ABC_FULL_CACHE(1) | S_028ABC_PIPE_ALIGNED(1) |
6924 ds->db_htile_surface = 0;
6976 ds->db_htile_surface = S_028ABC_FULL_CACHE(1) | S_028ABC_PIPE_ALIGNED(1);
6979 ds->db_htile_surface |= S_028ABC_RB_ALIGNED(1);
6983 ds->db_htile_surface |= S_028ABC_VRS_HTILE_ENCODING(V_028ABC_VRS_HTILE_4BIT_ENCODING);
7045 ds->db_htile_surface = S_028ABC_FULL_CACHE(1);
7050 ds->db_htile_surface |= S_028ABC_TC_COMPATIBLE(1);
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| H A D | radv_private.h | 1275 uint32_t db_htile_surface; member in struct:radv_ds_buffer_info
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| H A D | radv_cmd_buffer.c | 1896 radeon_set_context_reg(cmd_buffer->cs, R_028ABC_DB_HTILE_SURFACE, ds->db_htile_surface);
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