Searched refs:display_dcc_offset (Results 1 - 17 of 17) sorted by relevance

/xsrc/external/mit/MesaLib/dist/src/amd/common/
H A Dac_surface_modifier_test.c127 _mesa_sha1_update(&ctx, &surf->display_dcc_offset, sizeof(surf->display_dcc_offset));
153 if (surf->display_dcc_offset) {
188 if (surf->display_dcc_offset) {
288 assert(surf.display_dcc_offset == expected_offset);
292 assert(!surf.display_dcc_offset);
H A Dac_surface.c2403 surf->meta_offset = surf->display_dcc_offset = surf->fmask_offset = surf->cmask_offset = 0;
2432 surf->display_dcc_offset = align64(surf->total_size, 1 << surf->u.gfx9.color.display_dcc_alignment_log2);
2433 surf->total_size = surf->display_dcc_offset + surf->u.gfx9.color.display_dcc_size;
2451 surf->display_dcc_offset = 0;
2561 dcc_offset = surf->display_dcc_offset ? surf->display_dcc_offset : surf->meta_offset;
2838 if (surf->display_dcc_offset)
2839 surf->display_dcc_offset += offset;
2847 else if (surf->display_dcc_offset)
2870 return surf->display_dcc_offset
[all...]
H A Dac_surface.h381 uint64_t display_dcc_offset; member in struct:radeon_surf
/xsrc/external/mit/MesaLib/dist/src/gallium/drivers/radeonsi/
H A Dsi_compute_blit.c605 assert(tex->surface.display_dcc_offset && tex->surface.display_dcc_offset <= UINT_MAX);
606 assert(tex->surface.display_dcc_offset < tex->surface.meta_offset);
611 sb.buffer_offset = tex->surface.display_dcc_offset;
614 sctx->cs_user_data[0] = tex->surface.meta_offset - tex->surface.display_dcc_offset;
H A Dsi_texture.c1096 if (tex->surface.display_dcc_offset && !(surface->flags & RADEON_SURF_IMPORTED)) {
1100 si_init_buffer_clear(&clears[num_clears++], &tex->buffer.b.b, tex->surface.display_dcc_offset,
H A Dsi_blit.c1342 if (tex->surface.display_dcc_offset && tex->displayable_dcc_dirty) {
H A Dsi_descriptors.c833 if (tex->surface.display_dcc_offset && view->access & PIPE_IMAGE_ACCESS_WRITE) {
H A Dsi_state.c2719 if (!tex->surface.display_dcc_offset || tex->displayable_dcc_dirty)
/xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/radeonsi/
H A Dsi_compute_blit.c455 assert(tex->display_dcc_offset && tex->display_dcc_offset <= UINT_MAX);
473 img[2].u.buf.offset = tex->display_dcc_offset;
H A Dsi_texture.c435 assert(tex->display_dcc_offset == 0);
443 tex->display_dcc_offset = 0;
633 tex->display_dcc_offset ? tex->display_dcc_offset
774 tex->display_dcc_offset)
1306 tex->display_dcc_offset =
1308 tex->size = tex->display_dcc_offset +
H A Dsi_pipe.h293 uint64_t display_dcc_offset; member in struct:si_texture
H A Dsi_blit.c1322 if (tex->display_dcc_offset)
/xsrc/external/mit/MesaLib/dist/src/amd/vulkan/
H A Dradv_meta_dcc_retile.c233 .offset = image->planes[0].surface.display_dcc_offset,
H A Dradv_image.c1270 (surface->display_dcc_offset ? surface->display_dcc_offset : surface->meta_offset);
H A Dradv_cmd_buffer.c7532 return image->planes[0].surface.display_dcc_offset &&
7533 image->planes[0].surface.display_dcc_offset != image->planes[0].surface.meta_offset;
/xsrc/external/mit/MesaLib/dist/docs/relnotes/
H A D20.0.0.rst2340 - radeonsi: remove the "display_dcc_offset == 0" assertion
H A D20.2.0.rst3236 - radeonsi: use display_dcc_offset for setting displayable_dcc_cb_mask

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