Searched refs:domains (Results 1 - 25 of 77) sorted by relevance

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/xsrc/external/mit/MesaLib/dist/src/gallium/drivers/zink/
H A Dzink_bo.h126 VkMemoryPropertyFlags domains = 0; local in function:vk_domain_from_heap
131 domains = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT;
134 domains = VK_MEMORY_PROPERTY_LAZILY_ALLOCATED_BIT | VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT;
137 domains = VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT | VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT;
140 domains = VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT | VK_MEMORY_PROPERTY_HOST_COHERENT_BIT;
143 domains = VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT | VK_MEMORY_PROPERTY_HOST_CACHED_BIT;
148 return domains;
152 zink_heap_from_domain_flags(VkMemoryPropertyFlags domains, enum zink_alloc_flag flags) argument
157 if ((domains & VK_VIS_VRAM) == VK_VIS_VRAM)
160 if (domains
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/xsrc/external/mit/libdrm/dist/radeon/
H A Dradeon_bo_int.h16 uint32_t domains; member in struct:radeon_bo_int
29 uint32_t domains,
H A Dradeon_bo_gem.c64 uint32_t domains,
79 bo->base.domains = domains;
102 args.initial_domain = bo->base.domains;
112 fprintf(stderr, " domains : %d\n", bo->base.domains);
382 bo->base.domains = RADEON_GEM_DOMAIN_GTT;
60 bo_open(struct radeon_bo_manager * bom,uint32_t handle,uint32_t size,uint32_t alignment,uint32_t domains,uint32_t flags) argument
H A Dradeon_bo.h58 uint32_t domains,
H A Dradeon_bo.c46 uint32_t alignment, uint32_t domains, uint32_t flags)
49 bo = bom->funcs->bo_open(bom, handle, size, alignment, domains, flags);
45 radeon_bo_open(struct radeon_bo_manager * bom,uint32_t handle,uint32_t size,uint32_t alignment,uint32_t domains,uint32_t flags) argument
/xsrc/external/mit/libdrm/dist/etnaviv/
H A Detnaviv_perfmon.c85 list_addtail(&dom->head, &pm->domains);
117 LIST_FOR_EACH_ENTRY_SAFE(dom, next, &pm->domains, head) {
135 list_inithead(&pm->domains);
138 /* query all available domains and sources for this device */
164 LIST_FOR_EACH_ENTRY(dom, &pm->domains, head) {
H A Detnaviv_priv.h159 struct list_head domains; member in struct:etna_perfmon
/xsrc/external/mit/MesaLib/dist/src/etnaviv/drm/
H A Detnaviv_perfmon.c85 list_addtail(&dom->head, &pm->domains);
117 LIST_FOR_EACH_ENTRY_SAFE(dom, next, &pm->domains, head) {
135 list_inithead(&pm->domains);
138 /* query all available domains and sources for this device */
164 LIST_FOR_EACH_ENTRY(dom, &pm->domains, head) {
H A Detnaviv_priv.h169 struct list_head domains; member in struct:etna_perfmon
/xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/r600/
H A Dr600_buffer_common.c123 res->domains = RADEON_DOMAIN_GTT;
131 res->domains = RADEON_DOMAIN_GTT;
141 res->domains = RADEON_DOMAIN_VRAM;
159 res->domains = RADEON_DOMAIN_GTT;
165 res->domains = RADEON_DOMAIN_VRAM;
183 if (res->domains & RADEON_DOMAIN_VRAM)
185 else if (res->domains & RADEON_DOMAIN_GTT)
197 res->domains, res->flags);
287 assert(rdst->domains == rsrc->domains);
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H A Dr600_cs.h79 rbo->domains, priority) * 4;
/xsrc/external/mit/MesaLib/dist/src/gallium/drivers/r600/
H A Dr600_buffer_common.c124 res->domains = RADEON_DOMAIN_GTT;
131 res->domains = RADEON_DOMAIN_GTT;
141 res->domains = RADEON_DOMAIN_VRAM;
158 res->domains = RADEON_DOMAIN_GTT;
164 res->domains = RADEON_DOMAIN_VRAM;
182 if (res->domains & RADEON_DOMAIN_VRAM)
184 else if (res->domains & RADEON_DOMAIN_GTT)
196 res->domains, res->flags);
285 assert(rdst->domains == rsrc->domains);
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/xsrc/external/mit/xf86-video-amdgpu/dist/src/
H A Damdgpu_bo_helper.h52 * \param domains - \c [in] GEM domains
60 uint32_t domains);
H A Damdgpu_bo_helper.c293 uint32_t domains)
306 alloc_request.preferred_heap = domains;
290 amdgpu_bo_open(amdgpu_device_handle pDev,uint32_t alloc_size,uint32_t phys_alignment,uint32_t domains) argument
/xsrc/external/mit/libdrm/dist/nouveau/
H A Dpushbuf.c81 uint32_t *domains)
94 if (*domains == NOUVEAU_GEM_DOMAIN_VRAM) {
113 if ((*domains & NOUVEAU_GEM_DOMAIN_VRAM) &&
115 *domains &= NOUVEAU_GEM_DOMAIN_VRAM;
156 uint32_t domains, domains_wr, domains_rd; local in function:pushbuf_kref
158 domains = 0;
160 domains |= NOUVEAU_GEM_DOMAIN_VRAM;
162 domains |= NOUVEAU_GEM_DOMAIN_GART;
163 domains_wr = domains * !!(flags & NOUVEAU_BO_WR);
164 domains_rd = domains * !!(flag
80 pushbuf_kref_fits(struct nouveau_pushbuf * push,struct nouveau_bo * bo,uint32_t * domains) argument
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/xsrc/external/mit/MesaLib/dist/src/gallium/drivers/radeonsi/
H A Dsi_buffer.c60 res->domains = RADEON_DOMAIN_VRAM;
62 res->domains = RADEON_DOMAIN_GTT;
67 res->domains = RADEON_DOMAIN_GTT;
74 res->domains = RADEON_DOMAIN_GTT;
84 res->domains = RADEON_DOMAIN_VRAM;
102 res->domains = RADEON_DOMAIN_GTT;
108 res->domains = RADEON_DOMAIN_VRAM;
150 if (res->domains & RADEON_DOMAIN_VRAM) {
171 res->domains, res->flags);
293 assert(sdst->domains
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/xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/radeonsi/
H A Dsi_buffer.c122 res->domains = RADEON_DOMAIN_GTT;
129 res->domains = RADEON_DOMAIN_GTT;
139 res->domains = RADEON_DOMAIN_VRAM;
159 res->domains = RADEON_DOMAIN_GTT;
165 res->domains = RADEON_DOMAIN_VRAM;
191 if (res->domains & RADEON_DOMAIN_VRAM) {
198 } else if (res->domains & RADEON_DOMAIN_GTT) {
211 res->domains, res->flags);
320 assert(sdst->domains == ssrc->domains);
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H A Dsi_dma_cs.c188 dst->domains, 0);
192 src->domains, 0);
/xsrc/external/mit/MesaLib/dist/src/freedreno/rnn/
H A Dheadergen2.c495 if (db->domains[i]->size)
496 printdef (db->domains[i]->fullname, "SIZE", 0, db->domains[i]->size, db->domains[i]->file);
498 for (j = 0; j < db->domains[i]->subelemsnum; j++) {
499 printdelem(db->domains[i]->subelems[j], 0, NULL);
H A Drnn.h58 struct rnndomain **domains; member in struct:rnndb
/xsrc/external/mit/MesaLib/dist/docs/_exts/
H A Dnir.py28 from sphinx.domains import Domain
/xsrc/external/mit/MesaLib/dist/src/amd/vulkan/winsys/amdgpu/
H A Dradv_amdgpu_bo.c523 fprintf(stderr, "amdgpu: domains : %u\n", initial_domain);
807 radv_amdgpu_bo_get_flags_from_fd(struct radeon_winsys *_ws, int fd, enum radeon_bo_domain *domains, argument
815 *domains = 0;
828 *domains |= RADEON_DOMAIN_VRAM;
830 *domains |= RADEON_DOMAIN_GTT;
832 *domains |= RADEON_DOMAIN_GDS;
834 *domains |= RADEON_DOMAIN_OA;
/xsrc/external/mit/xf86-video-openchrome/dist/src/
H A Dvia_drm.h320 uint32_t domains; member in struct:drm_via_gem_object
H A Dvia_memmgr.c149 args.domains = domain;
/xsrc/external/mit/MesaLib.old/dist/src/gallium/winsys/radeon/drm/
H A Dradeon_drm_cs.c39 based on the domains, which are simply or'd for the accounting purposes.
41 accounts any newly-referenced domains.
336 enum radeon_bo_domain domains,
348 domains |= RADEON_DOMAIN_GTT;
350 enum radeon_bo_domain rd = usage & RADEON_USAGE_READ ? domains : 0;
351 enum radeon_bo_domain wd = usage & RADEON_USAGE_WRITE ? domains : 0;
333 radeon_drm_cs_add_buffer(struct radeon_cmdbuf * rcs,struct pb_buffer * buf,enum radeon_bo_usage usage,enum radeon_bo_domain domains,enum radeon_bo_priority priority) argument

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