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    Searched refs:ge_cntl (Results 1 - 4 of 4) sorted by relevancy

  /xsrc/external/mit/MesaLib/dist/src/gallium/drivers/radeonsi/
si_state_draw.cpp 1197 /* GFX10 removed IA_MULTI_VGT_PARAM in exchange for GE_CNTL.
1204 unsigned ge_cntl;
1208 ge_cntl = S_03096C_PRIM_GRP_SIZE(num_patches) |
1212 ge_cntl = si_get_vs_inline(sctx, HAS_TESS, HAS_GS)->current->ge_cntl;
1230 ge_cntl = S_03096C_PRIM_GRP_SIZE(primgroup_size) | S_03096C_VERT_GRP_SIZE(vertgroup_size) |
1234 ge_cntl |= S_03096C_PACKET_TO_ONE_PA(si_is_line_stipple_enabled(sctx));
1236 if (ge_cntl != sctx->last_multi_vgt_param) {
1240 radeon_set_uconfig_reg(R_03096C_GE_CNTL, ge_cntl);
1242 sctx->last_multi_vgt_param = ge_cntl;
    [all...]
si_shader.h 881 unsigned ge_cntl; member in struct:si_shader
si_state_shaders.c 1311 shader->ge_cntl = S_03096C_PRIM_GRP_SIZE(shader->ngg.max_gsprims) |
1321 * Tessellation is unaffected because it always sets GE_CNTL.VERT_GRP_SIZE = 0.
1330 shader->ge_cntl &= C_03096C_VERT_GRP_SIZE;
1331 shader->ge_cntl |= S_03096C_VERT_GRP_SIZE(shader->ngg.hw_max_esverts - 5);
  /xsrc/external/mit/MesaLib/dist/src/amd/vulkan/
radv_pipeline.c 2033 * of GE_CNTL.VERT_GRP_SIZE based on based on the primitive type of
4535 unsigned ge_cntl; local
4599 ge_cntl = S_03096C_PRIM_GRP_SIZE(ngg_state->max_gsprims) |
4604 * Tessellation always sets GE_CNTL.VERT_GRP_SIZE = 0
4606 * Requirement: GE_CNTL.VERT_GRP_SIZE = VGT_GS_ONCHIP_CNTL.ES_VERTS_PER_SUBGRP - 5
4610 ge_cntl &= C_03096C_VERT_GRP_SIZE;
4613 ge_cntl |= S_03096C_VERT_GRP_SIZE(ngg_state->hw_max_esverts - 5);
4617 radeon_set_uconfig_reg(ctx_cs, R_03096C_GE_CNTL, ge_cntl);

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