Searched refs:gen7 (Results 1 - 25 of 48) sorted by relevance

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/xsrc/external/mit/MesaLib.old/dist/src/intel/vulkan/
H A Dgen7_cmd_buffer.c142 cmd_buffer->state.gfx.gen7.index_buffer = buffer;
143 cmd_buffer->state.gfx.gen7.index_type = vk_to_gen_index_type[indexType];
144 cmd_buffer->state.gfx.gen7.index_offset = offset;
198 anv_batch_emit_merge(&cmd_buffer->batch, sf_dw, pipeline->gen7.sf);
243 pipeline->gen7.depth_stencil_state,
252 if (cmd_buffer->state.gfx.gen7.index_buffer &&
255 struct anv_buffer *buffer = cmd_buffer->state.gfx.gen7.index_buffer;
256 uint32_t offset = cmd_buffer->state.gfx.gen7.index_offset;
269 ib.IndexFormat = cmd_buffer->state.gfx.gen7.index_type;
287 /* The NP PMA fix doesn't exist on gen7 */
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/xsrc/external/mit/xf86-video-intel/dist/src/sna/
H A Dgen7_render.c97 .name = "Ivybridge (gen7)",
106 .name = "Ivybridge (gen7, gt1)",
116 .name = "Ivybridge (gen7, gt2)",
126 .name = "Baytrail (gen7)",
135 .name = "Haswell (gen7.5)",
146 .name = "Haswell (gen7.5, gt1)",
158 .name = "Haswell (gen7.5, gt2)",
170 .name = "Haswell (gen7.5, gt3)",
540 OUT_BATCH(sna->render_state.gen7.info->urb.push_ps_size);
544 OUT_BATCH((sna->render_state.gen7
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/xsrc/external/mit/xf86-video-intel-2014/dist/src/sna/
H A Dgen7_render.c99 .name = "Ivybridge (gen7)",
108 .name = "Ivybridge (gen7, gt1)",
118 .name = "Ivybridge (gen7, gt2)",
128 .name = "Baytrail (gen7)",
137 .name = "Haswell (gen7.5)",
148 .name = "Haswell (gen7.5, gt1)",
160 .name = "Haswell (gen7.5, gt2)",
172 .name = "Haswell (gen7.5, gt3)",
503 OUT_BATCH(sna->render_state.gen7.info->urb.push_ps_size);
507 OUT_BATCH((sna->render_state.gen7
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/xsrc/external/mit/MesaLib.old/dist/src/intel/
H A DAndroid.genxml.mk80 $(intermediates)/genxml/gen7_pack.h: PRIVATE_XML := $(LOCAL_PATH)/genxml/gen7.xml
81 $(intermediates)/genxml/gen7_pack.h: $(LOCAL_PATH)/genxml/gen7.xml $(LOCAL_PATH)/genxml/gen_pack_header.py
H A DAndroid.vulkan.mk119 # libanv for gen7
H A DMakefile.sources140 genxml/gen7.xml \
/xsrc/external/mit/MesaLib/dist/docs/relnotes/
H A D10.2.rst39 - GL_ARB_texture_view on i965/gen7
H A D17.0.7.rst102 - intel/isl/gen7: Use stencil vertical alignment of 8 instead of 4
H A D19.0.3.rst76 - anv/pipeline: Fix MEDIA_VFE_STATE::PerThreadScratchSpace on gen7
H A D19.0.7.rst81 - anv: Set STATE_BASE_ADDRESS upper bounds on gen7
H A D19.1.1.rst82 - anv: Set STATE_BASE_ADDRESS upper bounds on gen7
H A D19.1.4.rst138 - anv: Disable transform feedback on gen7
142 - intel/fs: Implement quad_swap_horizontal with a swizzle on gen7
H A D9.1.3.rst118 - i965/fs: Do CSE on gen7's varying-index pull constant loads.
120 - i965/gen7: Skip resetting SOL offsets at batch start with HW
H A D10.0.5.rst147 - i965/gen7: Prefer vertical alignment of 4 when possible.
H A D13.0.2.rst112 - anv: Implement a depth stall restriction on gen7
H A D17.1.1.rst128 - intel/isl/gen7: Use stencil vertical alignment of 8 instead of 4
H A D17.1.7.rst102 - anv/formats: Allow sampling on depth-only formats on gen7
H A D19.1.2.rst158 - anv/cmd_buffer: Reuse gen8 Cmd{Set, Reset}Event on gen7
H A D8.0.1.rst106 - i965/fs: Enable register spilling on gen7 too.
H A D10.3.rst38 - GL_ARB_gpu_shader5 on i965/gen7, nvc0
45 - GL_ARB_texture_compression_bptc on i965/gen7+, nvc0, r600/evergreen+,
53 - GL_AMD_vertex_shader_viewport_index on i965/gen7+, r600
H A D11.2.2.rst165 - i965/blorp/gen7: Prepare re-using for gen8
H A D13.0.5.rst146 - anv: Flush render cache before STATE_BASE_ADDRESS on gen7
H A D17.0.1.rst119 - i965/sampler_state: Clamp min/max LOD to 14 on gen7+
H A D17.1.4.rst63 - i965: Add and initialize l3_banks field for gen7+
H A D18.3.2.rst152 - intel/eu/gen7: Fix brw_MOV() with DF destination and strided source.

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