| /xsrc/external/mit/MesaLib.old/dist/src/amd/vulkan/ |
| H A D | radv_device.c | 2091 uint32_t gsvs_ring_size,
2151 desc[2] = gsvs_ring_size;
2305 uint32_t gsvs_ring_size)
2319 radeon_emit(cs, gsvs_ring_size >> 8);
2323 radeon_emit(cs, gsvs_ring_size >> 8);
2452 uint32_t gsvs_ring_size,
2490 gsvs_ring_size <= queue->gsvs_ring_size &&
2496 if (!scratch_size && !compute_scratch_size && !esgs_ring_size && !gsvs_ring_size)
2540 if (gsvs_ring_size > queu
2086 fill_geom_tess_rings(struct radv_queue * queue,uint32_t * map,bool add_sample_positions,uint32_t esgs_ring_size,struct radeon_winsys_bo * esgs_ring_bo,uint32_t gsvs_ring_size,struct radeon_winsys_bo * gsvs_ring_bo,uint32_t tess_factor_ring_size,uint32_t tess_offchip_ring_offset,uint32_t tess_offchip_ring_size,struct radeon_winsys_bo * tess_rings_bo) argument
2301 radv_emit_gs_ring_sizes(struct radv_queue * queue,struct radeon_cmdbuf * cs,struct radeon_winsys_bo * esgs_ring_bo,uint32_t esgs_ring_size,struct radeon_winsys_bo * gsvs_ring_bo,uint32_t gsvs_ring_size) argument
2448 radv_get_preamble_cs(struct radv_queue * queue,uint32_t scratch_size,uint32_t compute_scratch_size,uint32_t esgs_ring_size,uint32_t gsvs_ring_size,bool needs_tess_rings,bool needs_sample_positions,struct radeon_cmdbuf ** initial_full_flush_preamble_cs,struct radeon_cmdbuf ** initial_preamble_cs,struct radeon_cmdbuf ** continue_preamble_cs) argument
2920 uint32_t esgs_ring_size = 0, gsvs_ring_size = 0; local in function:radv_QueueSubmit
[all...] |
| H A D | radv_private.h | 649 uint32_t gsvs_ring_size; member in struct:radv_queue
1395 unsigned gsvs_ring_size; member in struct:radv_pipeline::__anone2cea0a71a0a::__anone2cea0a71b08
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| H A D | radv_pipeline.c | 1580 unsigned gsvs_ring_size = max_gs_waves * 2 * wave_size * local in function:calculate_gs_ring_sizes
1585 gsvs_ring_size = align(gsvs_ring_size, alignment);
1590 pipeline->graphics.gsvs_ring_size = MIN2(gsvs_ring_size, max_size);
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| H A D | radv_cmd_buffer.c | 3047 if (pipeline->graphics.gsvs_ring_size > cmd_buffer->gsvs_ring_size_needed)
3048 cmd_buffer->gsvs_ring_size_needed = pipeline->graphics.gsvs_ring_size;
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| /xsrc/external/mit/MesaLib/dist/src/amd/vulkan/ |
| H A D | radv_device.c | 3373 uint32_t gsvs_ring_size, struct radeon_winsys_bo *gsvs_ring_bo,
3427 desc[2] = gsvs_ring_size;
3583 struct radeon_winsys_bo *gsvs_ring_bo, uint32_t gsvs_ring_size)
3597 radeon_emit(cs, gsvs_ring_size >> 8);
3601 radeon_emit(cs, gsvs_ring_size >> 8);
3746 uint32_t gsvs_ring_size, bool needs_tess_rings, bool needs_gds,
3807 esgs_ring_size <= queue->esgs_ring_size && gsvs_ring_size <= queue->gsvs_ring_size &&
3814 !gsvs_ring_size && !needs_tess_rings && !needs_gds && !needs_gds_oa &&
3855 if (gsvs_ring_size > queu
3371 fill_geom_tess_rings(struct radv_queue * queue,uint32_t * map,bool add_sample_positions,uint32_t esgs_ring_size,struct radeon_winsys_bo * esgs_ring_bo,uint32_t gsvs_ring_size,struct radeon_winsys_bo * gsvs_ring_bo,uint32_t tess_factor_ring_size,uint32_t tess_offchip_ring_offset,uint32_t tess_offchip_ring_size,struct radeon_winsys_bo * tess_rings_bo) argument
3581 radv_emit_gs_ring_sizes(struct radv_queue * queue,struct radeon_cmdbuf * cs,struct radeon_winsys_bo * esgs_ring_bo,uint32_t esgs_ring_size,struct radeon_winsys_bo * gsvs_ring_bo,uint32_t gsvs_ring_size) argument
3743 radv_get_preamble_cs(struct radv_queue * queue,uint32_t scratch_size_per_wave,uint32_t scratch_waves,uint32_t compute_scratch_size_per_wave,uint32_t compute_scratch_waves,uint32_t esgs_ring_size,uint32_t gsvs_ring_size,bool needs_tess_rings,bool needs_gds,bool needs_gds_oa,bool needs_sample_positions,struct radeon_cmdbuf ** initial_full_flush_preamble_cs,struct radeon_cmdbuf ** initial_preamble_cs,struct radeon_cmdbuf ** continue_preamble_cs) argument
4399 uint32_t esgs_ring_size = 0, gsvs_ring_size = 0; local in function:radv_get_preambles
[all...] |
| H A D | radv_private.h | 674 uint32_t gsvs_ring_size; member in struct:radv_queue
1800 unsigned gsvs_ring_size; member in struct:radv_pipeline::__anon4674665a290a::__anon4674665a2a08
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| H A D | radv_pipeline.c | 2241 unsigned gsvs_ring_size = max_gs_waves * 2 * wave_size * gs_info->gs.max_gsvs_emit_size; local in function:radv_pipeline_init_gs_ring_state
2245 gsvs_ring_size = align(gsvs_ring_size, alignment);
2250 pipeline->graphics.gsvs_ring_size = MIN2(gsvs_ring_size, max_size);
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| H A D | radv_cmd_buffer.c | 4927 if (pipeline->graphics.gsvs_ring_size > cmd_buffer->gsvs_ring_size_needed)
4928 cmd_buffer->gsvs_ring_size_needed = pipeline->graphics.gsvs_ring_size;
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| /xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/radeonsi/ |
| H A D | si_state_shaders.c | 2932 unsigned gsvs_ring_size = max_gs_waves * 2 * wave_size * local in function:si_update_gs_ring_buffers
2937 gsvs_ring_size = align(gsvs_ring_size, alignment);
2940 gsvs_ring_size = MIN2(gsvs_ring_size, max_size);
2951 bool update_gsvs = gsvs_ring_size &&
2953 sctx->gsvs_ring->width0 < gsvs_ring_size);
2975 gsvs_ring_size, alignment);
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| /xsrc/external/mit/MesaLib/dist/src/gallium/drivers/radeonsi/ |
| H A D | si_state_shaders.c | 3591 unsigned gsvs_ring_size = max_gs_waves * 2 * wave_size * gs->max_gsvs_emit_size; local in function:si_update_gs_ring_buffers
3595 gsvs_ring_size = align(gsvs_ring_size, alignment);
3598 gsvs_ring_size = MIN2(gsvs_ring_size, max_size);
3608 gsvs_ring_size && (!sctx->gsvs_ring || sctx->gsvs_ring->width0 < gsvs_ring_size);
3630 gsvs_ring_size, sctx->screen->info.pte_fragment_size);
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