Searched refs:insn (Results 1 - 25 of 105) sorted by relevance

12345

/xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/nouveau/codegen/
H A Dnv50_ir_lowering_helper.cpp30 LoweringHelper::visit(Instruction *insn) argument
32 switch (insn->op) {
34 return handleABS(insn);
36 return handleCVT(insn);
39 return handleMAXMIN(insn);
41 return handleMOV(insn);
43 return handleNEG(insn);
45 return handleSAT(insn);
47 return handleSLCT(insn->asCmp());
52 return handleLogOp(insn);
59 handleABS(Instruction * insn) argument
83 handleCVT(Instruction * insn) argument
113 handleMAXMIN(Instruction * insn) argument
149 handleMOV(Instruction * insn) argument
177 handleNEG(Instruction * insn) argument
191 handleSAT(Instruction * insn) argument
208 handleSLCT(CmpInstruction * insn) argument
242 handleLogOp(Instruction * insn) argument
[all...]
H A Dnv50_ir_emit_gm107.cpp49 const Instruction *insn; member in class:nv50_ir::CodeEmitterGM107
106 emitRND(pos, insn->rnd, -1);
238 if (insn->predSrc >= 0) {
239 emitField(16, 3, insn->getSrc(insn->predSrc)->rep()->reg.data.id);
240 emitField(19, 1, insn->cc == CC_NOT_P);
328 if (isFloatType(insn->sType))
343 if (insn->sType == TYPE_F32 || insn->sType == TYPE_F16) {
346 } else if (insn
526 const FlowInstruction *insn = this->insn->asFlow(); local in function:nv50_ir::CodeEmitterGM107::emitBRA
563 const FlowInstruction *insn = this->insn->asFlow(); local in function:nv50_ir::CodeEmitterGM107::emitCAL
592 const FlowInstruction *insn = this->insn->asFlow(); local in function:nv50_ir::CodeEmitterGM107::emitPCNT
614 const FlowInstruction *insn = this->insn->asFlow(); local in function:nv50_ir::CodeEmitterGM107::emitPBK
636 const FlowInstruction *insn = this->insn->asFlow(); local in function:nv50_ir::CodeEmitterGM107::emitPRET
658 const FlowInstruction *insn = this->insn->asFlow(); local in function:nv50_ir::CodeEmitterGM107::emitSSY
1152 const CmpInstruction *insn = this->insn->asCmp(); local in function:nv50_ir::CodeEmitterGM107::emitDSET
1200 const CmpInstruction *insn = this->insn->asCmp(); local in function:nv50_ir::CodeEmitterGM107::emitDSETP
1493 const CmpInstruction *insn = this->insn->asCmp(); local in function:nv50_ir::CodeEmitterGM107::emitFCMP
1539 const CmpInstruction *insn = this->insn->asCmp(); local in function:nv50_ir::CodeEmitterGM107::emitFSET
1588 const CmpInstruction *insn = this->insn->asCmp(); local in function:nv50_ir::CodeEmitterGM107::emitFSETP
1992 const CmpInstruction *insn = this->insn->asCmp(); local in function:nv50_ir::CodeEmitterGM107::emitICMP
2038 const CmpInstruction *insn = this->insn->asCmp(); local in function:nv50_ir::CodeEmitterGM107::emitISET
2084 const CmpInstruction *insn = this->insn->asCmp(); local in function:nv50_ir::CodeEmitterGM107::emitISETP
2823 const TexInstruction *insn = this->insn->asTex(); local in function:nv50_ir::CodeEmitterGM107::emitTEX
2865 const TexInstruction *insn = this->insn->asTex(); local in function:nv50_ir::CodeEmitterGM107::emitTEXS
2909 const TexInstruction *insn = this->insn->asTex(); local in function:nv50_ir::CodeEmitterGM107::emitTLD
2934 const TexInstruction *insn = this->insn->asTex(); local in function:nv50_ir::CodeEmitterGM107::emitTLD4
2964 const TexInstruction *insn = this->insn->asTex(); local in function:nv50_ir::CodeEmitterGM107::emitTXD
2987 const TexInstruction *insn = this->insn->asTex(); local in function:nv50_ir::CodeEmitterGM107::emitTMML
3010 const TexInstruction *insn = this->insn->asTex(); local in function:nv50_ir::CodeEmitterGM107::emitTXQ
3198 const TexInstruction *insn = this->insn->asTex(); local in function:nv50_ir::CodeEmitterGM107::emitSUTarget
3225 const TexInstruction *insn = this->insn->asTex(); local in function:nv50_ir::CodeEmitterGM107::emitSUHandle
3242 const TexInstruction *insn = this->insn->asTex(); local in function:nv50_ir::CodeEmitterGM107::emitSUSTx
3260 const TexInstruction *insn = this->insn->asTex(); local in function:nv50_ir::CodeEmitterGM107::emitSULDx
3290 const TexInstruction *insn = this->insn->asTex(); local in function:nv50_ir::CodeEmitterGM107::emitSUREDx
3840 LiveBarUse(Instruction * insn,Instruction * usei) argument
3842 Instruction *insn; member in struct:nv50_ir::SchedDataCalculatorGM107::LiveBarUse
3847 LiveBarDef(Instruction * insn,Instruction * defi) argument
3849 Instruction *insn; member in struct:nv50_ir::SchedDataCalculatorGM107::LiveBarDef
3864 emitStall(Instruction * insn,uint8_t cnt) argument
3871 emitYield(Instruction * insn) argument
3877 emitWrDepBar(Instruction * insn,uint8_t id) argument
3886 emitRdDepBar(Instruction * insn,uint8_t id) argument
3895 emitWtDepBar(Instruction * insn,uint8_t id) argument
3902 emitReuse(Instruction * insn,uint8_t id) argument
3957 setReuseFlag(Instruction * insn) argument
4041 commitInsn(const Instruction * insn,int cycle) argument
4057 calcDelay(const Instruction * insn,int cycle) const argument
4070 setDelay(Instruction * insn,int delay,const Instruction * next) argument
4188 doesInsnWriteTo(const Instruction * insn,const Value * val) const argument
4231 Instruction *insn, *next; local in function:nv50_ir::SchedDataCalculatorGM107::findFirstUse
4255 Instruction *insn, *next; local in function:nv50_ir::SchedDataCalculatorGM107::findFirstDef
4281 Instruction *insn, *next; local in function:nv50_ir::SchedDataCalculatorGM107::insertBarriers
4403 Instruction *insn, *next = NULL; local in function:nv50_ir::SchedDataCalculatorGM107::visit
4406 for (Instruction *insn = bb->getEntry(); insn; insn = insn->next) { local in function:nv50_ir::SchedDataCalculatorGM107::visit
[all...]
H A Dnv50_ir_target_gm107.cpp84 TargetGM107::isReuseSupported(const Instruction *insn) const
86 const OpClass cl = getOpClass(insn->op);
97 if (insn->op == OP_INSBF || insn->op == OP_EXTBF)
111 TargetGM107::isBarrierRequired(const Instruction *insn) const
113 const OpClass cl = getOpClass(insn->op);
115 if (insn->dType == TYPE_F64 || insn->sType == TYPE_F64)
126 switch (insn->op) {
142 switch (insn
[all...]
H A Dnv50_ir_bb.cpp239 BasicBlock::remove(Instruction *insn) argument
241 assert(insn->bb == this);
243 if (insn->prev)
244 insn->prev->next = insn->next;
246 if (insn->next)
247 insn->next->prev = insn->prev;
249 exit = insn->prev;
251 if (insn
299 splitCommon(Instruction * insn,BasicBlock * bb,bool attach) argument
330 splitBefore(Instruction * insn,bool attach) argument
343 splitAfter(Instruction * insn,bool attach) argument
425 for (Instruction *insn = bb->getFirst(); insn; insn = insn->next) local in function:nv50_ir::Function::orderInstructions
485 Instruction *insn, *next; local in function:nv50_ir::Pass::doRun
[all...]
H A Dnv50_ir_build_util.cpp68 Instruction *insn = new_Instruction(func, op, ty); local in function:nv50_ir::BuildUtil::mkOp1
70 insn->setDef(0, dst);
71 insn->setSrc(0, src);
73 insert(insn);
74 return insn;
81 Instruction *insn = new_Instruction(func, op, ty); local in function:nv50_ir::BuildUtil::mkOp2
83 insn->setDef(0, dst);
84 insn->setSrc(0, src0);
85 insn->setSrc(1, src1);
87 insert(insn);
95 Instruction *insn = new_Instruction(func, op, ty); local in function:nv50_ir::BuildUtil::mkOp3
109 Instruction *insn = new_Instruction(func, OP_LOAD, ty); local in function:nv50_ir::BuildUtil::mkLoad
124 Instruction *insn = new_Instruction(func, op, ty); local in function:nv50_ir::BuildUtil::mkStore
141 Instruction *insn = mkOp1(OP_VFETCH, ty, dst, sym); local in function:nv50_ir::BuildUtil::mkFetch
164 Instruction *insn = mkOp1(op, ty, dst, sym); local in function:nv50_ir::BuildUtil::mkInterp
173 Instruction *insn = new_Instruction(func, OP_MOV, ty); local in function:nv50_ir::BuildUtil::mkMov
185 Instruction *insn = new_Instruction(func, OP_MOV, typeOfSize(src->reg.size)); local in function:nv50_ir::BuildUtil::mkMovToReg
198 Instruction *insn = new_Instruction(func, OP_MOV, typeOfSize(dst->reg.size)); local in function:nv50_ir::BuildUtil::mkMovFromReg
212 Instruction *insn = new_Instruction(func, op, dstTy); local in function:nv50_ir::BuildUtil::mkCvt
226 CmpInstruction *insn = new_CmpInstruction(func, op); local in function:nv50_ir::BuildUtil::mkCmp
287 Instruction *insn = NULL; local in function:nv50_ir::BuildUtil::mkSplit
312 FlowInstruction *insn = new_FlowInstruction(func, op, targ); local in function:nv50_ir::BuildUtil::mkFlow
340 Instruction *insn = mkOp(OP_NOP, TYPE_NONE, NULL); local in function:nv50_ir::BuildUtil::mkClobber
[all...]
H A Dnv50_ir_from_nir.cpp249 Converter::getDType(nir_alu_instr *insn) argument
251 if (insn->dest.dest.is_ssa)
252 return getDType(insn->op, insn->dest.dest.ssa.bit_size);
254 return getDType(insn->op, insn->dest.dest.reg.reg->bit_size);
258 Converter::getDType(nir_intrinsic_instr *insn) argument
261 switch (insn->intrinsic) {
273 return getDType(insn, isSigned);
277 Converter::getDType(nir_intrinsic_instr *insn, boo argument
297 getSTypes(nir_alu_instr * insn) argument
792 getIndirect(nir_intrinsic_instr * insn,uint8_t s,uint8_t c,Value * & indirect) argument
1385 getSlotAddress(nir_intrinsic_instr * insn,uint8_t idx,uint8_t slot) argument
1472 storeTo(nir_intrinsic_instr * insn,DataFile file,operation op,DataType ty,Value * src,uint8_t idx,uint8_t c,Value * indirect0,Value * indirect1) argument
1736 Instruction *insn = bb->getExit(); local in function:__anon42ea91d60110::Converter::visit
1755 visit(nir_instr * insn) argument
1908 visit(nir_intrinsic_instr * insn) argument
2620 visit(nir_jump_instr * insn) argument
2647 convert(nir_load_const_instr * insn,uint8_t idx) argument
2677 visit(nir_load_const_instr * insn) argument
2694 visit(nir_alu_instr * insn) argument
3091 visit(nir_ssa_undef_instr * insn) argument
3226 visit(nir_tex_instr * insn) argument
[all...]
H A Dnv50_ir_peephole.cpp191 LoadPropagation::checkSwapSrc01(Instruction *insn) argument
194 if (!targ->getOpInfo(insn).commutative) {
195 if (insn->op != OP_SET && insn->op != OP_SLCT &&
196 insn->op != OP_SUB && insn->op != OP_XMAD)
199 if (insn->op == OP_XMAD &&
200 (insn->subOp & NV50_IR_SUBOP_XMAD_CMODE_MASK) == NV50_IR_SUBOP_XMAD_CBCC)
202 if (insn->op == OP_XMAD && (insn
316 Instruction *insn; local in function:nv50_ir::IndirectPropagation::visit
444 Instruction *insn = value->getInsn(); local in function:nv50_ir::ConstantFolding::findOriginForTestWithZero
877 Instruction *insn; local in function:nv50_ir::ConstantFolding::tryCollapseChainedMULs
993 Instruction *insn = bld.mkOp3(OP_SHLADD, TYPE_U32, res, a, bld.mkImm(shl), a); local in function:nv50_ir::ConstantFolding::createMul
2042 Instruction *insn = cvt->getSrc(0)->getInsn(); local in function:nv50_ir::AlgebraicOpt::handleCVT_NEG
2082 Instruction *insn = cvt->getSrc(0)->getInsn(); local in function:nv50_ir::AlgebraicOpt::handleCVT_CVT
2128 Instruction *insn = cvt->getSrc(0)->getInsn(); local in function:nv50_ir::AlgebraicOpt::handleCVT_EXTBF
2220 handleSUCLAMP(Instruction * insn) argument
2474 Instruction *insn = bld.mkOp3(OP_XMAD, TYPE_U32, tmp0, b, a, c); local in function:nv50_ir::LateAlgebraicOpt::handleMULMAD
2648 Instruction *insn; member in class:nv50_ir::MemoryOpt::Record
2882 getList(const Instruction * insn) argument
2902 findRecord(const Instruction * insn,bool load,bool & isAdj) const argument
3226 Instruction *insn = pred->getUniqueInsn(); local in function:nv50_ir::FlatteningPass::isConstantCondition
3259 removeFlow(Instruction * insn) argument
3299 mayPredicate(const Instruction * insn,const Value * pred) const argument
3371 Instruction *insn = bb->getExit(); local in function:nv50_ir::FlatteningPass::visit
3402 Instruction *insn; local in function:nv50_ir::FlatteningPass::tryPredicateConditional
[all...]
/xsrc/external/mit/MesaLib/dist/src/gallium/drivers/nouveau/codegen/
H A Dnv50_ir_lowering_helper.cpp30 LoweringHelper::visit(Instruction *insn) argument
32 switch (insn->op) {
34 return handleABS(insn);
36 return handleCVT(insn);
39 return handleMAXMIN(insn);
41 return handleMOV(insn);
43 return handleNEG(insn);
45 return handleSAT(insn);
47 return handleSLCT(insn->asCmp());
52 return handleLogOp(insn);
59 handleABS(Instruction * insn) argument
83 handleCVT(Instruction * insn) argument
113 handleMAXMIN(Instruction * insn) argument
149 handleMOV(Instruction * insn) argument
177 handleNEG(Instruction * insn) argument
191 handleSAT(Instruction * insn) argument
208 handleSLCT(CmpInstruction * insn) argument
242 handleLogOp(Instruction * insn) argument
[all...]
H A Dnv50_ir_emit_gm107.cpp50 const Instruction *insn; member in class:nv50_ir::CodeEmitterGM107
107 emitRND(pos, insn->rnd, -1);
242 if (insn->predSrc >= 0) {
243 emitField(16, 3, insn->getSrc(insn->predSrc)->rep()->reg.data.id);
244 emitField(19, 1, insn->cc == CC_NOT_P);
332 if (isFloatType(insn->sType))
347 if (insn->sType == TYPE_F32 || insn->sType == TYPE_F16) {
350 } else if (insn
530 const FlowInstruction *insn = this->insn->asFlow(); local in function:nv50_ir::CodeEmitterGM107::emitBRA
567 const FlowInstruction *insn = this->insn->asFlow(); local in function:nv50_ir::CodeEmitterGM107::emitCAL
596 const FlowInstruction *insn = this->insn->asFlow(); local in function:nv50_ir::CodeEmitterGM107::emitPCNT
618 const FlowInstruction *insn = this->insn->asFlow(); local in function:nv50_ir::CodeEmitterGM107::emitPBK
640 const FlowInstruction *insn = this->insn->asFlow(); local in function:nv50_ir::CodeEmitterGM107::emitPRET
662 const FlowInstruction *insn = this->insn->asFlow(); local in function:nv50_ir::CodeEmitterGM107::emitSSY
1190 const CmpInstruction *insn = this->insn->asCmp(); local in function:nv50_ir::CodeEmitterGM107::emitDSET
1238 const CmpInstruction *insn = this->insn->asCmp(); local in function:nv50_ir::CodeEmitterGM107::emitDSETP
1531 const CmpInstruction *insn = this->insn->asCmp(); local in function:nv50_ir::CodeEmitterGM107::emitFCMP
1577 const CmpInstruction *insn = this->insn->asCmp(); local in function:nv50_ir::CodeEmitterGM107::emitFSET
1626 const CmpInstruction *insn = this->insn->asCmp(); local in function:nv50_ir::CodeEmitterGM107::emitFSETP
2030 const CmpInstruction *insn = this->insn->asCmp(); local in function:nv50_ir::CodeEmitterGM107::emitICMP
2076 const CmpInstruction *insn = this->insn->asCmp(); local in function:nv50_ir::CodeEmitterGM107::emitISET
2122 const CmpInstruction *insn = this->insn->asCmp(); local in function:nv50_ir::CodeEmitterGM107::emitISETP
2888 const TexInstruction *insn = this->insn->asTex(); local in function:nv50_ir::CodeEmitterGM107::emitTEX
2930 const TexInstruction *insn = this->insn->asTex(); local in function:nv50_ir::CodeEmitterGM107::emitTEXS
2974 const TexInstruction *insn = this->insn->asTex(); local in function:nv50_ir::CodeEmitterGM107::emitTLD
2999 const TexInstruction *insn = this->insn->asTex(); local in function:nv50_ir::CodeEmitterGM107::emitTLD4
3029 const TexInstruction *insn = this->insn->asTex(); local in function:nv50_ir::CodeEmitterGM107::emitTXD
3052 const TexInstruction *insn = this->insn->asTex(); local in function:nv50_ir::CodeEmitterGM107::emitTMML
3075 const TexInstruction *insn = this->insn->asTex(); local in function:nv50_ir::CodeEmitterGM107::emitTXQ
3263 const TexInstruction *insn = this->insn->asTex(); local in function:nv50_ir::CodeEmitterGM107::emitSUTarget
3290 const TexInstruction *insn = this->insn->asTex(); local in function:nv50_ir::CodeEmitterGM107::emitSUHandle
3307 const TexInstruction *insn = this->insn->asTex(); local in function:nv50_ir::CodeEmitterGM107::emitSUSTx
3325 const TexInstruction *insn = this->insn->asTex(); local in function:nv50_ir::CodeEmitterGM107::emitSULDx
3355 const TexInstruction *insn = this->insn->asTex(); local in function:nv50_ir::CodeEmitterGM107::emitSUREDx
3787 emitStall(Instruction * insn,uint8_t cnt) argument
3794 emitYield(Instruction * insn) argument
3800 emitWrDepBar(Instruction * insn,uint8_t id) argument
3809 emitRdDepBar(Instruction * insn,uint8_t id) argument
3818 emitWtDepBar(Instruction * insn,uint8_t id) argument
3825 emitReuse(Instruction * insn,uint8_t id) argument
3880 setReuseFlag(Instruction * insn) argument
3964 commitInsn(const Instruction * insn,int cycle) argument
3980 calcDelay(const Instruction * insn,int cycle) const argument
3993 setDelay(Instruction * insn,int delay,const Instruction * next) argument
4111 doesInsnWriteTo(const Instruction * insn,const Value * val) const argument
4154 Instruction *insn, *next; local in function:nv50_ir::SchedDataCalculatorGM107::findFirstUse
4178 Instruction *insn, *next; local in function:nv50_ir::SchedDataCalculatorGM107::findFirstDef
4204 Instruction *insn, *next; local in function:nv50_ir::SchedDataCalculatorGM107::insertBarriers
4326 Instruction *insn, *next = NULL; local in function:nv50_ir::SchedDataCalculatorGM107::visit
4329 for (Instruction *insn = bb->getEntry(); insn; insn = insn->next) { local in function:nv50_ir::SchedDataCalculatorGM107::visit
[all...]
H A Dnv50_ir_emit_gv100.cpp51 emitIMMD(32, 32, insn->src(src));
52 if (insn->src(src).mod.abs())
54 if (insn->src(src).mod.neg())
65 emitGPR (64, insn->src(src1 & FA_SRC_MASK));
70 emitCBUF(54, -1, 38, 0, 2, insn->src(src2 & FA_SRC_MASK));
81 emitGPR (64, insn->src(src1 & FA_SRC_MASK));
94 emitGPR (64, insn->src(src2 & FA_SRC_MASK));
100 emitGPR (32, insn->src(src1 & FA_SRC_MASK));
108 switch ((src1 < 0) ? FILE_GPR : insn->src(src1 & FA_SRC_MASK).getFile()) {
110 switch ((src2 < 0) ? FILE_GPR : insn
161 const FlowInstruction *insn = this->insn->asFlow(); local in function:nv50_ir::CodeEmitterGV100::emitBRA
513 const CmpInstruction *insn = this->insn->asCmp(); local in function:nv50_ir::CodeEmitterGV100::emitFSET_BF
538 const CmpInstruction *insn = this->insn->asCmp(); local in function:nv50_ir::CodeEmitterGV100::emitFSETP
639 const CmpInstruction *insn = this->insn->asCmp(); local in function:nv50_ir::CodeEmitterGV100::emitDSETP
735 const CmpInstruction *insn = this->insn->asCmp(); local in function:nv50_ir::CodeEmitterGV100::emitISETP
1199 const TexInstruction *insn = this->insn->asTex(); local in function:nv50_ir::CodeEmitterGV100::emitTEX
1243 const TexInstruction *insn = this->insn->asTex(); local in function:nv50_ir::CodeEmitterGV100::emitTLD
1271 const TexInstruction *insn = this->insn->asTex(); local in function:nv50_ir::CodeEmitterGV100::emitTLD4
1308 const TexInstruction *insn = this->insn->asTex(); local in function:nv50_ir::CodeEmitterGV100::emitTMML
1333 const TexInstruction *insn = this->insn->asTex(); local in function:nv50_ir::CodeEmitterGV100::emitTXD
1359 const TexInstruction *insn = this->insn->asTex(); local in function:nv50_ir::CodeEmitterGV100::emitTXQ
1394 const TexInstruction *insn = this->insn->asTex(); local in function:nv50_ir::CodeEmitterGV100::emitSUHandle
1413 const TexInstruction *insn = this->insn->asTex(); local in function:nv50_ir::CodeEmitterGV100::emitSUTarget
1440 const TexInstruction *insn = this->insn->asTex(); local in function:nv50_ir::CodeEmitterGV100::emitSUATOM
1485 const TexInstruction *insn = this->insn->asTex(); local in function:nv50_ir::CodeEmitterGV100::emitSULD
1523 const TexInstruction *insn = this->insn->asTex(); local in function:nv50_ir::CodeEmitterGV100::emitSUST
[all...]
H A Dnv50_ir_target_gm107.cpp84 TargetGM107::isReuseSupported(const Instruction *insn) const
86 const OpClass cl = getOpClass(insn->op);
97 if (insn->op == OP_INSBF || insn->op == OP_EXTBF)
111 TargetGM107::isBarrierRequired(const Instruction *insn) const
113 const OpClass cl = getOpClass(insn->op);
115 if (insn->dType == TYPE_F64 || insn->sType == TYPE_F64)
126 switch (insn->op) {
142 switch (insn
[all...]
H A Dnv50_ir_bb.cpp239 BasicBlock::remove(Instruction *insn) argument
241 assert(insn->bb == this);
243 if (insn->prev)
244 insn->prev->next = insn->next;
246 if (insn->next)
247 insn->next->prev = insn->prev;
249 exit = insn->prev;
251 if (insn
299 splitCommon(Instruction * insn,BasicBlock * bb,bool attach) argument
330 splitBefore(Instruction * insn,bool attach) argument
343 splitAfter(Instruction * insn,bool attach) argument
425 for (Instruction *insn = bb->getFirst(); insn; insn = insn->next) local in function:nv50_ir::Function::orderInstructions
485 Instruction *insn, *next; local in function:nv50_ir::Pass::doRun
[all...]
H A Dnv50_ir_build_util.cpp70 Instruction *insn = new_Instruction(func, op, ty); local in function:nv50_ir::BuildUtil::mkOp1
72 insn->setDef(0, dst);
73 insn->setSrc(0, src);
75 insert(insn);
76 return insn;
83 Instruction *insn = new_Instruction(func, op, ty); local in function:nv50_ir::BuildUtil::mkOp2
85 insn->setDef(0, dst);
86 insn->setSrc(0, src0);
87 insn->setSrc(1, src1);
89 insert(insn);
97 Instruction *insn = new_Instruction(func, op, ty); local in function:nv50_ir::BuildUtil::mkOp3
111 Instruction *insn = new_Instruction(func, OP_LOAD, ty); local in function:nv50_ir::BuildUtil::mkLoad
126 Instruction *insn = new_Instruction(func, op, ty); local in function:nv50_ir::BuildUtil::mkStore
143 Instruction *insn = mkOp1(OP_VFETCH, ty, dst, sym); local in function:nv50_ir::BuildUtil::mkFetch
166 Instruction *insn = mkOp1(op, ty, dst, sym); local in function:nv50_ir::BuildUtil::mkInterp
175 Instruction *insn = new_Instruction(func, OP_MOV, ty); local in function:nv50_ir::BuildUtil::mkMov
187 Instruction *insn = new_Instruction(func, OP_MOV, typeOfSize(src->reg.size)); local in function:nv50_ir::BuildUtil::mkMovToReg
200 Instruction *insn = new_Instruction(func, OP_MOV, typeOfSize(dst->reg.size)); local in function:nv50_ir::BuildUtil::mkMovFromReg
214 Instruction *insn = new_Instruction(func, op, dstTy); local in function:nv50_ir::BuildUtil::mkCvt
228 CmpInstruction *insn = new_CmpInstruction(func, op); local in function:nv50_ir::BuildUtil::mkCmp
289 Instruction *insn = NULL; local in function:nv50_ir::BuildUtil::mkSplit
314 FlowInstruction *insn = new_FlowInstruction(func, op, targ); local in function:nv50_ir::BuildUtil::mkFlow
342 Instruction *insn = mkOp(OP_NOP, TYPE_NONE, NULL); local in function:nv50_ir::BuildUtil::mkClobber
[all...]
H A Dnv50_ir_from_nir.cpp261 Converter::getDType(nir_alu_instr *insn) argument
263 if (insn->dest.dest.is_ssa)
264 return getDType(insn->op, insn->dest.dest.ssa.bit_size);
266 return getDType(insn->op, insn->dest.dest.reg.reg->bit_size);
270 Converter::getDType(nir_intrinsic_instr *insn) argument
273 switch (insn->intrinsic) {
295 if (insn->dest.is_ssa)
296 return typeOfSize(insn
313 getSTypes(nir_alu_instr * insn) argument
843 getIndirect(nir_intrinsic_instr * insn,uint8_t s,uint8_t c,Value * & indirect,bool isScalar) argument
1175 getSlotAddress(nir_intrinsic_instr * insn,uint8_t idx,uint8_t slot) argument
1262 storeTo(nir_intrinsic_instr * insn,DataFile file,operation op,DataType ty,Value * src,uint8_t idx,uint8_t c,Value * indirect0,Value * indirect1) argument
1534 visit(nir_instr * insn) argument
1626 visit(nir_intrinsic_instr * insn) argument
2396 visit(nir_jump_instr * insn) argument
2422 convert(nir_load_const_instr * insn,uint8_t idx) argument
2452 visit(nir_load_const_instr * insn) argument
2469 visit(nir_alu_instr * insn) argument
2866 visit(nir_ssa_undef_instr * insn) argument
2937 visit(nir_tex_instr * insn) argument
[all...]
H A Dnv50_ir_peephole.cpp191 LoadPropagation::checkSwapSrc01(Instruction *insn) argument
194 if (!targ->getOpInfo(insn).commutative) {
195 if (insn->op != OP_SET && insn->op != OP_SLCT &&
196 insn->op != OP_SUB && insn->op != OP_XMAD)
199 if (insn->op == OP_XMAD &&
200 (insn->subOp & NV50_IR_SUBOP_XMAD_CMODE_MASK) == NV50_IR_SUBOP_XMAD_CBCC)
202 if (insn->op == OP_XMAD && (insn
318 Instruction *insn; local in function:nv50_ir::IndirectPropagation::visit
447 Instruction *insn = value->getInsn(); local in function:nv50_ir::ConstantFolding::findOriginForTestWithZero
910 Instruction *insn; local in function:nv50_ir::ConstantFolding::tryCollapseChainedMULs
1026 Instruction *insn = bld.mkOp3(OP_SHLADD, TYPE_U32, res, a, bld.mkImm(shl), a); local in function:nv50_ir::ConstantFolding::createMul
2095 Instruction *insn = cvt->getSrc(0)->getInsn(); local in function:nv50_ir::AlgebraicOpt::handleCVT_NEG
2135 Instruction *insn = cvt->getSrc(0)->getInsn(); local in function:nv50_ir::AlgebraicOpt::handleCVT_CVT
2181 Instruction *insn = cvt->getSrc(0)->getInsn(); local in function:nv50_ir::AlgebraicOpt::handleCVT_EXTBF
2273 handleSUCLAMP(Instruction * insn) argument
2527 Instruction *insn = bld.mkOp3(OP_XMAD, TYPE_U32, tmp0, b, a, c); local in function:nv50_ir::LateAlgebraicOpt::handleMULMAD
2701 Instruction *insn; member in class:nv50_ir::MemoryOpt::Record
2945 getList(const Instruction * insn) argument
2965 findRecord(const Instruction * insn,bool load,bool & isAdj) const argument
3300 Instruction *insn = pred->getUniqueInsn(); local in function:nv50_ir::FlatteningPass::isConstantCondition
3333 removeFlow(Instruction * insn) argument
3373 mayPredicate(const Instruction * insn,const Value * pred) const argument
3445 Instruction *insn = bb->getExit(); local in function:nv50_ir::FlatteningPass::visit
3476 Instruction *insn; local in function:nv50_ir::FlatteningPass::tryPredicateConditional
[all...]
/xsrc/external/mit/xf86-video-intel/dist/src/sna/brw/
H A Dbrw_eu_emit.c44 struct brw_instruction *insn,
48 insn->header.execution_size = BRW_EXECUTE_16;
50 insn->header.execution_size = reg.width;
100 brw_set_dest(struct brw_compile *p, struct brw_instruction *insn, argument
109 insn->bits1.da1.dest_reg_file = dest.file;
110 insn->bits1.da1.dest_reg_type = dest.type;
111 insn->bits1.da1.dest_address_mode = dest.address_mode;
114 insn->bits1.da1.dest_reg_nr = dest.nr;
116 if (insn->header.access_mode == BRW_ALIGN_1) {
117 insn
43 guess_execution_size(struct brw_compile * p,struct brw_instruction * insn,struct brw_reg reg) argument
159 validate_reg(struct brw_instruction * insn,struct brw_reg reg) argument
235 brw_set_src0(struct brw_compile * p,struct brw_instruction * insn,struct brw_reg reg) argument
305 brw_set_src1(struct brw_compile * p,struct brw_instruction * insn,struct brw_reg reg) argument
411 brw_set_math_message(struct brw_compile * p,struct brw_instruction * insn,unsigned function,unsigned integer_type,bool low_precision,bool saturate,unsigned dataType) argument
465 brw_set_ff_sync_message(struct brw_compile * p,struct brw_instruction * insn,bool allocate,unsigned response_length,bool end_of_thread) argument
482 brw_set_urb_message(struct brw_compile * p,struct brw_instruction * insn,bool allocate,bool used,unsigned msg_length,unsigned response_length,bool end_of_thread,bool complete,unsigned offset,unsigned swizzle_control) argument
521 brw_set_dp_write_message(struct brw_compile * p,struct brw_instruction * insn,unsigned binding_table_index,unsigned msg_control,unsigned msg_type,unsigned msg_length,bool header_present,bool last_render_target,unsigned response_length,bool end_of_thread,bool send_commit_msg) argument
579 brw_set_dp_read_message(struct brw_compile * p,struct brw_instruction * insn,unsigned binding_table_index,unsigned msg_control,unsigned msg_type,unsigned target_cache,unsigned msg_length,unsigned response_length) argument
634 brw_set_sampler_message(struct brw_compile * p,struct brw_instruction * insn,unsigned binding_table_index,unsigned sampler,unsigned msg_type,unsigned response_length,unsigned msg_length,bool header_present,unsigned simd_mode) argument
673 struct brw_instruction *insn = brw_next_insn(p, BRW_OPCODE_NOP); local in function:brw_NOP
711 struct brw_instruction *insn; local in function:brw_IF
753 struct brw_instruction *insn; local in function:gen6_IF
896 struct brw_instruction *insn; local in function:brw_ELSE
928 struct brw_instruction *insn; local in function:brw_ENDIF
981 struct brw_instruction *insn; local in function:brw_BREAK
1004 struct brw_instruction *insn; local in function:gen6_CONT
1020 struct brw_instruction *insn; local in function:brw_CONT
1054 struct brw_instruction *insn = brw_next_insn(p, BRW_OPCODE_DO); local in function:brw_DO
1075 struct brw_instruction *insn; local in function:brw_WHILE
1157 struct brw_instruction *insn = brw_next_insn(p, BRW_OPCODE_CMP); local in function:brw_CMP
1179 struct brw_instruction *insn = brw_next_insn(p, BRW_OPCODE_WAIT); local in function:brw_WAIT
1206 struct brw_instruction *insn = brw_next_insn(p, BRW_OPCODE_MATH); local in function:brw_math
1233 struct brw_instruction *insn = brw_next_insn(p, BRW_OPCODE_SEND); local in function:brw_math
1258 struct brw_instruction *insn = brw_next_insn(p, BRW_OPCODE_MATH); local in function:brw_math2
1302 struct brw_instruction *insn; local in function:brw_math_16
1407 struct brw_instruction *insn = brw_next_insn(p, BRW_OPCODE_SEND); local in function:brw_oword_block_write_scratch
1510 struct brw_instruction *insn = brw_next_insn(p, BRW_OPCODE_SEND); local in function:brw_oword_block_read_scratch
1545 struct brw_instruction *insn; local in function:brw_oword_block_read
1601 struct brw_instruction *insn; local in function:brw_dword_scattered_read
1641 struct brw_instruction *insn; local in function:brw_dp_READ_4_vs
1692 struct brw_instruction *insn; local in function:brw_dp_READ_4_vs_relative
1748 struct brw_instruction *insn; local in function:brw_fb_WRITE
1831 struct brw_instruction *insn; local in function:brw_SAMPLE
1871 struct brw_instruction *insn; local in function:brw_urb_WRITE
1914 struct brw_instruction *insn = &p->store[ip]; local in function:brw_find_next_block_end
1938 struct brw_instruction *insn = &p->store[ip]; local in function:brw_find_loop_end
1964 struct brw_instruction *insn = &p->store[ip]; local in function:brw_set_uip_jip
1992 struct brw_instruction *insn; local in function:brw_ff_sync
[all...]
/xsrc/external/mit/xf86-video-intel-2014/dist/src/sna/brw/
H A Dbrw_eu_emit.c44 struct brw_instruction *insn,
48 insn->header.execution_size = BRW_EXECUTE_16;
50 insn->header.execution_size = reg.width;
100 brw_set_dest(struct brw_compile *p, struct brw_instruction *insn, argument
109 insn->bits1.da1.dest_reg_file = dest.file;
110 insn->bits1.da1.dest_reg_type = dest.type;
111 insn->bits1.da1.dest_address_mode = dest.address_mode;
114 insn->bits1.da1.dest_reg_nr = dest.nr;
116 if (insn->header.access_mode == BRW_ALIGN_1) {
117 insn
43 guess_execution_size(struct brw_compile * p,struct brw_instruction * insn,struct brw_reg reg) argument
159 validate_reg(struct brw_instruction * insn,struct brw_reg reg) argument
235 brw_set_src0(struct brw_compile * p,struct brw_instruction * insn,struct brw_reg reg) argument
305 brw_set_src1(struct brw_compile * p,struct brw_instruction * insn,struct brw_reg reg) argument
411 brw_set_math_message(struct brw_compile * p,struct brw_instruction * insn,unsigned function,unsigned integer_type,bool low_precision,bool saturate,unsigned dataType) argument
465 brw_set_ff_sync_message(struct brw_compile * p,struct brw_instruction * insn,bool allocate,unsigned response_length,bool end_of_thread) argument
482 brw_set_urb_message(struct brw_compile * p,struct brw_instruction * insn,bool allocate,bool used,unsigned msg_length,unsigned response_length,bool end_of_thread,bool complete,unsigned offset,unsigned swizzle_control) argument
521 brw_set_dp_write_message(struct brw_compile * p,struct brw_instruction * insn,unsigned binding_table_index,unsigned msg_control,unsigned msg_type,unsigned msg_length,bool header_present,bool last_render_target,unsigned response_length,bool end_of_thread,bool send_commit_msg) argument
579 brw_set_dp_read_message(struct brw_compile * p,struct brw_instruction * insn,unsigned binding_table_index,unsigned msg_control,unsigned msg_type,unsigned target_cache,unsigned msg_length,unsigned response_length) argument
634 brw_set_sampler_message(struct brw_compile * p,struct brw_instruction * insn,unsigned binding_table_index,unsigned sampler,unsigned msg_type,unsigned response_length,unsigned msg_length,bool header_present,unsigned simd_mode) argument
673 struct brw_instruction *insn = brw_next_insn(p, BRW_OPCODE_NOP); local in function:brw_NOP
711 struct brw_instruction *insn; local in function:brw_IF
753 struct brw_instruction *insn; local in function:gen6_IF
896 struct brw_instruction *insn; local in function:brw_ELSE
928 struct brw_instruction *insn; local in function:brw_ENDIF
981 struct brw_instruction *insn; local in function:brw_BREAK
1004 struct brw_instruction *insn; local in function:gen6_CONT
1020 struct brw_instruction *insn; local in function:brw_CONT
1054 struct brw_instruction *insn = brw_next_insn(p, BRW_OPCODE_DO); local in function:brw_DO
1075 struct brw_instruction *insn; local in function:brw_WHILE
1157 struct brw_instruction *insn = brw_next_insn(p, BRW_OPCODE_CMP); local in function:brw_CMP
1179 struct brw_instruction *insn = brw_next_insn(p, BRW_OPCODE_WAIT); local in function:brw_WAIT
1206 struct brw_instruction *insn = brw_next_insn(p, BRW_OPCODE_MATH); local in function:brw_math
1233 struct brw_instruction *insn = brw_next_insn(p, BRW_OPCODE_SEND); local in function:brw_math
1258 struct brw_instruction *insn = brw_next_insn(p, BRW_OPCODE_MATH); local in function:brw_math2
1302 struct brw_instruction *insn; local in function:brw_math_16
1407 struct brw_instruction *insn = brw_next_insn(p, BRW_OPCODE_SEND); local in function:brw_oword_block_write_scratch
1510 struct brw_instruction *insn = brw_next_insn(p, BRW_OPCODE_SEND); local in function:brw_oword_block_read_scratch
1545 struct brw_instruction *insn; local in function:brw_oword_block_read
1601 struct brw_instruction *insn; local in function:brw_dword_scattered_read
1641 struct brw_instruction *insn; local in function:brw_dp_READ_4_vs
1692 struct brw_instruction *insn; local in function:brw_dp_READ_4_vs_relative
1748 struct brw_instruction *insn; local in function:brw_fb_WRITE
1831 struct brw_instruction *insn; local in function:brw_SAMPLE
1871 struct brw_instruction *insn; local in function:brw_urb_WRITE
1914 struct brw_instruction *insn = &p->store[ip]; local in function:brw_find_next_block_end
1938 struct brw_instruction *insn = &p->store[ip]; local in function:brw_find_loop_end
1964 struct brw_instruction *insn = &p->store[ip]; local in function:brw_set_uip_jip
1992 struct brw_instruction *insn; local in function:brw_ff_sync
[all...]
/xsrc/external/mit/MesaLib/dist/src/intel/compiler/
H A Dbrw_eu_emit.c518 brw_inst *insn,
525 brw_set_desc(p, insn, brw_message_desc(
528 brw_inst_set_sfid(devinfo, insn, BRW_SFID_URB);
529 brw_inst_set_eot(devinfo, insn, end_of_thread);
530 brw_inst_set_urb_opcode(devinfo, insn, 1); /* FF_SYNC */
531 brw_inst_set_urb_allocate(devinfo, insn, allocate);
533 brw_inst_set_urb_global_offset(devinfo, insn, 0);
534 brw_inst_set_urb_swizzle_control(devinfo, insn, 0);
535 brw_inst_set_urb_used(devinfo, insn, 0);
536 brw_inst_set_urb_complete(devinfo, insn,
517 brw_set_ff_sync_message(struct brw_codegen * p,brw_inst * insn,bool allocate,unsigned response_length,bool end_of_thread) argument
539 brw_set_urb_message(struct brw_codegen * p,brw_inst * insn,enum brw_urb_write_flags flags,unsigned msg_length,unsigned response_length,unsigned offset,unsigned swizzle_control) argument
613 brw_inst_set_state(const struct intel_device_info * devinfo,brw_inst * insn,const struct brw_insn_state * state) argument
698 brw_inst *insn = brw_append_insns(p, 1, sizeof(brw_inst)); local in function:brw_next_insn
732 brw_inst *insn = next_insn(p, opcode); local in function:brw_alu1
746 brw_inst *insn = next_insn(p, opcode); local in function:brw_alu2
1332 brw_inst *insn = next_insn(p, BRW_OPCODE_NOP); local in function:brw_NOP
1339 brw_inst *insn = next_insn(p, BRW_OPCODE_SYNC); local in function:brw_SYNC
1422 brw_inst *insn; local in function:brw_IF
1471 brw_inst *insn; local in function:gfx6_IF
1625 brw_inst *insn; local in function:brw_ELSE
1664 brw_inst *insn = NULL; local in function:brw_ENDIF
1745 brw_inst *insn; local in function:brw_BREAK
1772 brw_inst *insn; local in function:brw_CONT
1796 brw_inst *insn; local in function:brw_HALT
1846 brw_inst *insn = next_insn(p, BRW_OPCODE_DO); local in function:brw_DO
1900 brw_inst *insn, *do_insn; local in function:brw_WHILE
1988 brw_inst *insn = next_insn(p, BRW_OPCODE_CMP); local in function:brw_CMP
2017 brw_inst *insn = next_insn(p, BRW_OPCODE_CMPN); local in function:brw_CMPN
2054 brw_inst *insn = next_insn(p, BRW_OPCODE_SEND); local in function:gfx4_math
2087 brw_inst *insn = next_insn(p, BRW_OPCODE_MATH); local in function:gfx6_math
2206 brw_inst *insn = next_insn(p, BRW_OPCODE_SEND); local in function:brw_oword_block_write_scratch
2319 brw_inst *insn = next_insn(p, BRW_OPCODE_SEND); local in function:brw_oword_block_read_scratch
2348 brw_inst *insn = next_insn(p, BRW_OPCODE_SEND); local in function:gfx7_block_read_scratch
2422 brw_inst *insn = next_insn(p, BRW_OPCODE_SEND); local in function:brw_oword_block_read
2463 brw_inst *insn; local in function:brw_fb_WRITE
2512 brw_inst *insn = next_insn(p, BRW_OPCODE_SENDC); local in function:gfx9_fb_READ
2546 brw_inst *insn; local in function:brw_SAMPLE
2645 brw_inst *insn; local in function:brw_urb_WRITE
2890 while_jumps_before_offset(const struct intel_device_info * devinfo,brw_inst * insn,int while_offset,int start_offset) argument
2913 brw_inst *insn = store + offset; local in function:brw_find_next_block_end
2963 brw_inst *insn = store + offset; local in function:brw_find_loop_end
2990 brw_inst *insn = store + offset; local in function:brw_set_uip_jip
3059 brw_inst *insn; local in function:brw_ff_sync
3100 brw_inst *insn; local in function:brw_svb_write
3216 brw_set_memory_fence_message(struct brw_codegen * p,struct brw_inst * insn,enum brw_message_target sfid,bool commit_enable,unsigned bti) argument
3248 gfx12_set_memory_fence_message(struct brw_codegen * p,struct brw_inst * insn,enum brw_message_target sfid) argument
3293 struct brw_inst *insn = next_insn(p, send_op); local in function:brw_memory_fence
3680 struct brw_inst *insn; local in function:brw_WAIT
[all...]
/xsrc/external/mit/MesaLib.old/dist/src/intel/compiler/
H A Dbrw_eu_emit.c482 brw_inst *insn,
489 brw_set_desc(p, insn, brw_message_desc(
492 brw_inst_set_sfid(devinfo, insn, BRW_SFID_URB);
493 brw_inst_set_eot(devinfo, insn, end_of_thread);
494 brw_inst_set_urb_opcode(devinfo, insn, 1); /* FF_SYNC */
495 brw_inst_set_urb_allocate(devinfo, insn, allocate);
497 brw_inst_set_urb_global_offset(devinfo, insn, 0);
498 brw_inst_set_urb_swizzle_control(devinfo, insn, 0);
499 brw_inst_set_urb_used(devinfo, insn, 0);
500 brw_inst_set_urb_complete(devinfo, insn,
481 brw_set_ff_sync_message(struct brw_codegen * p,brw_inst * insn,bool allocate,unsigned response_length,bool end_of_thread) argument
503 brw_set_urb_message(struct brw_codegen * p,brw_inst * insn,enum brw_urb_write_flags flags,unsigned msg_length,unsigned response_length,unsigned offset,unsigned swizzle_control) argument
577 brw_inst_set_state(const struct gen_device_info * devinfo,brw_inst * insn,const struct brw_insn_state * state) argument
610 brw_inst *insn; local in function:brw_next_insn
633 brw_inst *insn = next_insn(p, opcode); local in function:brw_alu1
647 brw_inst *insn = next_insn(p, opcode); local in function:brw_alu2
1215 brw_inst *insn = next_insn(p, BRW_OPCODE_NOP); local in function:brw_NOP
1303 brw_inst *insn; local in function:brw_IF
1351 brw_inst *insn; local in function:gen6_IF
1505 brw_inst *insn; local in function:brw_ELSE
1543 brw_inst *insn = NULL; local in function:brw_ENDIF
1624 brw_inst *insn; local in function:brw_BREAK
1651 brw_inst *insn; local in function:brw_CONT
1675 brw_inst *insn; local in function:gen6_HALT
1716 brw_inst *insn = next_insn(p, BRW_OPCODE_DO); local in function:brw_DO
1770 brw_inst *insn, *do_insn; local in function:brw_WHILE
1857 brw_inst *insn = next_insn(p, BRW_OPCODE_CMP); local in function:brw_CMP
1893 brw_inst *insn = next_insn(p, BRW_OPCODE_SEND); local in function:gen4_math
1926 brw_inst *insn = next_insn(p, BRW_OPCODE_MATH); local in function:gen6_math
2034 brw_inst *insn = next_insn(p, BRW_OPCODE_SEND); local in function:brw_oword_block_write_scratch
2144 brw_inst *insn = next_insn(p, BRW_OPCODE_SEND); local in function:brw_oword_block_read_scratch
2173 brw_inst *insn = next_insn(p, BRW_OPCODE_SEND); local in function:gen7_block_read_scratch
2242 brw_inst *insn = next_insn(p, BRW_OPCODE_SEND); local in function:brw_oword_block_read
2283 brw_inst *insn; local in function:brw_fb_WRITE
2339 brw_inst *insn = next_insn(p, BRW_OPCODE_SENDC); local in function:gen9_fb_READ
2375 brw_inst *insn; local in function:brw_SAMPLE
2471 brw_inst *insn; local in function:brw_urb_WRITE
2686 while_jumps_before_offset(const struct gen_device_info * devinfo,brw_inst * insn,int while_offset,int start_offset) argument
2709 brw_inst *insn = store + offset; local in function:brw_find_next_block_end
2756 brw_inst *insn = store + offset; local in function:brw_find_loop_end
2783 brw_inst *insn = store + offset; local in function:brw_set_uip_jip
2849 brw_inst *insn; local in function:brw_ff_sync
2892 brw_inst *insn; local in function:brw_svb_write
3010 brw_set_memory_fence_message(struct brw_codegen * p,struct brw_inst * insn,enum brw_message_target sfid,bool commit_enable) argument
3048 struct brw_inst *insn; local in function:brw_memory_fence
3449 struct brw_inst *insn; local in function:brw_WAIT
[all...]
/xsrc/external/mit/MesaLib/dist/src/intel/common/
H A Dintel_disasm.c48 const brw_inst *insn = assembly + offset; local in function:intel_disasm_find_end
50 if (brw_inst_cmpt_control(devinfo, insn)) {
57 uint32_t opcode = brw_inst_opcode(devinfo, insn);
58 if (opcode == 0 || (is_send(opcode) && brw_inst_eot(devinfo, insn))) {
/xsrc/external/mit/xf86-video-intel/dist/src/sna/
H A Dgen8_eu.c59 __gen8_bits(struct gen8_instruction *insn, unsigned high, unsigned low) argument
69 return (insn->data[word] >> low) & __gen8_mask(high, low);
78 __gen8_set_bits(struct gen8_instruction *insn, argument
93 insn->data[word] &= ~mask;
94 insn->data[word] |= (value << low) & mask;
96 assert(__gen8_bits(insn, 32*word+high, 32*word+low) == value);
100 static inline void __gen8_set_##name(struct gen8_instruction *insn, unsigned v) \
102 __gen8_set_bits(insn, high, low, v); \
104 static inline unsigned __gen8_##name(struct gen8_instruction *insn) \
106 return __gen8_bits(insn, hig
286 __gen8_set_uip(struct gen8_instruction * insn,unsigned uip) argument
291 __gen8_jip(struct gen8_instruction * insn) argument
296 __gen8_set_jip(struct gen8_instruction * insn,unsigned jip) argument
302 __gen8_src1_imm_d(struct gen8_instruction * insn) argument
307 __gen8_src1_imm_ud(struct gen8_instruction * insn) argument
312 __gen8_src1_imm_f(struct gen8_instruction * insn) argument
674 struct gen8_instruction *insn; local in function:gen8_next_insn
693 struct gen8_instruction *insn = gen8_next_insn(p, BRW_OPCODE_MATH); local in function:gen8_math
742 struct gen8_instruction *insn = gen8_next_insn(p, opcode); local in function:gen8_alu1
754 struct gen8_instruction *insn = gen8_next_insn(p, opcode); local in function:gen8_alu2
927 struct gen8_instruction *insn; local in function:gen8_SAMPLE
1047 struct gen8_instruction *insn; local in function:fb_write
1151 struct gen8_instruction *insn = memset(p->current, 0, sizeof(*insn)); local in function:gen8_compile_init
[all...]
/xsrc/external/mit/xf86-video-intel-2014/dist/src/sna/
H A Dgen8_eu.c59 __gen8_bits(struct gen8_instruction *insn, unsigned high, unsigned low) argument
69 return (insn->data[word] >> low) & __gen8_mask(high, low);
78 __gen8_set_bits(struct gen8_instruction *insn, argument
93 insn->data[word] &= ~mask;
94 insn->data[word] |= (value << low) & mask;
96 assert(__gen8_bits(insn, 32*word+high, 32*word+low) == value);
100 static inline void __gen8_set_##name(struct gen8_instruction *insn, unsigned v) \
102 __gen8_set_bits(insn, high, low, v); \
104 static inline unsigned __gen8_##name(struct gen8_instruction *insn) \
106 return __gen8_bits(insn, hig
286 __gen8_set_uip(struct gen8_instruction * insn,unsigned uip) argument
291 __gen8_jip(struct gen8_instruction * insn) argument
296 __gen8_set_jip(struct gen8_instruction * insn,unsigned jip) argument
302 __gen8_src1_imm_d(struct gen8_instruction * insn) argument
307 __gen8_src1_imm_ud(struct gen8_instruction * insn) argument
312 __gen8_src1_imm_f(struct gen8_instruction * insn) argument
674 struct gen8_instruction *insn; local in function:gen8_next_insn
693 struct gen8_instruction *insn = gen8_next_insn(p, BRW_OPCODE_MATH); local in function:gen8_math
742 struct gen8_instruction *insn = gen8_next_insn(p, opcode); local in function:gen8_alu1
754 struct gen8_instruction *insn = gen8_next_insn(p, opcode); local in function:gen8_alu2
927 struct gen8_instruction *insn; local in function:gen8_SAMPLE
1047 struct gen8_instruction *insn; local in function:fb_write
1151 struct gen8_instruction *insn = memset(p->current, 0, sizeof(*insn)); local in function:gen8_compile_init
[all...]
/xsrc/external/mit/MesaLib.old/dist/src/intel/common/
H A Dgen_disasm.c53 const brw_inst *insn = assembly + offset; local in function:gen_disasm_find_end
55 if (brw_inst_cmpt_control(devinfo, insn)) {
62 uint32_t opcode = brw_inst_opcode(devinfo, insn);
63 if (opcode == 0 || (is_send(opcode) && brw_inst_eot(devinfo, insn))) {
/xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/nouveau/nv30/
H A Dnvfx_fragprog.c86 fp->insn = realloc(fp->insn, sizeof(uint32_t) * fp->insn_len);
93 uint32_t *hw = &fp->insn[fpc->inst_offset];
111 hw = &fp->insn[fpc->inst_offset];
115 memcpy(&fp->insn[fpc->inst_offset + 4],
124 hw = &fp->insn[fpc->inst_offset];
136 memset(&fp->insn[fpd->offset], 0, sizeof(uint32_t) * 4);
166 uint32_t *hw = &fp->insn[fpc->inst_offset];
192 nvfx_fp_emit(struct nvfx_fpc *fpc, struct nvfx_insn insn) argument
200 hw = &fp->insn[fp
244 struct nvfx_insn insn = arith(0, MOV, none.reg, NVFX_FP_MASK_X, src, none, none); local in function:nv40_fp_if
450 struct nvfx_insn insn; local in function:nvfx_fragprog_parse_instruction
[all...]
/xsrc/external/mit/MesaLib/dist/src/gallium/drivers/nouveau/nv30/
H A Dnvfx_fragprog.c86 fp->insn = realloc(fp->insn, sizeof(uint32_t) * fp->insn_len);
93 uint32_t *hw = &fp->insn[fpc->inst_offset];
111 hw = &fp->insn[fpc->inst_offset];
115 memcpy(&fp->insn[fpc->inst_offset + 4],
124 hw = &fp->insn[fpc->inst_offset];
136 memset(&fp->insn[fpd->offset], 0, sizeof(uint32_t) * 4);
166 uint32_t *hw = &fp->insn[fpc->inst_offset];
192 nvfx_fp_emit(struct nvfx_fpc *fpc, struct nvfx_insn insn) argument
200 hw = &fp->insn[fp
244 struct nvfx_insn insn = arith(0, MOV, none.reg, NVFX_FP_MASK_X, src, none, none); local in function:nv40_fp_if
450 struct nvfx_insn insn; local in function:nvfx_fragprog_parse_instruction
[all...]

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